}
}
-static uint32_t r600_translate_colorswap(enum pipe_format format)
-{
- switch (format) {
- /* 8-bit buffers. */
- case PIPE_FORMAT_L4A4_UNORM:
- case PIPE_FORMAT_A4R4_UNORM:
- return V_028C70_SWAP_ALT;
-
- case PIPE_FORMAT_A8_UNORM:
- case PIPE_FORMAT_A8_SNORM:
- case PIPE_FORMAT_A8_UINT:
- case PIPE_FORMAT_A8_SINT:
- case PIPE_FORMAT_A16_UNORM:
- case PIPE_FORMAT_A16_SNORM:
- case PIPE_FORMAT_A16_UINT:
- case PIPE_FORMAT_A16_SINT:
- case PIPE_FORMAT_A16_FLOAT:
- case PIPE_FORMAT_A32_UINT:
- case PIPE_FORMAT_A32_SINT:
- case PIPE_FORMAT_A32_FLOAT:
- case PIPE_FORMAT_R4A4_UNORM:
- return V_028C70_SWAP_ALT_REV;
- case PIPE_FORMAT_I8_UNORM:
- case PIPE_FORMAT_I8_SNORM:
- case PIPE_FORMAT_I8_UINT:
- case PIPE_FORMAT_I8_SINT:
- case PIPE_FORMAT_I16_UNORM:
- case PIPE_FORMAT_I16_SNORM:
- case PIPE_FORMAT_I16_UINT:
- case PIPE_FORMAT_I16_SINT:
- case PIPE_FORMAT_I16_FLOAT:
- case PIPE_FORMAT_I32_UINT:
- case PIPE_FORMAT_I32_SINT:
- case PIPE_FORMAT_I32_FLOAT:
- case PIPE_FORMAT_L8_UNORM:
- case PIPE_FORMAT_L8_SNORM:
- case PIPE_FORMAT_L8_UINT:
- case PIPE_FORMAT_L8_SINT:
- case PIPE_FORMAT_L8_SRGB:
- case PIPE_FORMAT_L16_UNORM:
- case PIPE_FORMAT_L16_SNORM:
- case PIPE_FORMAT_L16_UINT:
- case PIPE_FORMAT_L16_SINT:
- case PIPE_FORMAT_L16_FLOAT:
- case PIPE_FORMAT_L32_UINT:
- case PIPE_FORMAT_L32_SINT:
- case PIPE_FORMAT_L32_FLOAT:
- case PIPE_FORMAT_R8_UNORM:
- case PIPE_FORMAT_R8_SNORM:
- case PIPE_FORMAT_R8_UINT:
- case PIPE_FORMAT_R8_SINT:
- return V_028C70_SWAP_STD;
-
- /* 16-bit buffers. */
- case PIPE_FORMAT_B5G6R5_UNORM:
- return V_028C70_SWAP_STD_REV;
-
- case PIPE_FORMAT_B5G5R5A1_UNORM:
- case PIPE_FORMAT_B5G5R5X1_UNORM:
- return V_028C70_SWAP_ALT;
-
- case PIPE_FORMAT_B4G4R4A4_UNORM:
- case PIPE_FORMAT_B4G4R4X4_UNORM:
- return V_028C70_SWAP_ALT;
-
- case PIPE_FORMAT_Z16_UNORM:
- return V_028C70_SWAP_STD;
-
- case PIPE_FORMAT_L8A8_UNORM:
- case PIPE_FORMAT_L8A8_SNORM:
- case PIPE_FORMAT_L8A8_UINT:
- case PIPE_FORMAT_L8A8_SINT:
- case PIPE_FORMAT_L8A8_SRGB:
- case PIPE_FORMAT_L16A16_UNORM:
- case PIPE_FORMAT_L16A16_SNORM:
- case PIPE_FORMAT_L16A16_UINT:
- case PIPE_FORMAT_L16A16_SINT:
- case PIPE_FORMAT_L16A16_FLOAT:
- case PIPE_FORMAT_L32A32_UINT:
- case PIPE_FORMAT_L32A32_SINT:
- case PIPE_FORMAT_L32A32_FLOAT:
- case PIPE_FORMAT_R8A8_UNORM:
- case PIPE_FORMAT_R8A8_SNORM:
- case PIPE_FORMAT_R8A8_UINT:
- case PIPE_FORMAT_R8A8_SINT:
- case PIPE_FORMAT_R16A16_UNORM:
- case PIPE_FORMAT_R16A16_SNORM:
- case PIPE_FORMAT_R16A16_UINT:
- case PIPE_FORMAT_R16A16_SINT:
- case PIPE_FORMAT_R16A16_FLOAT:
- case PIPE_FORMAT_R32A32_UINT:
- case PIPE_FORMAT_R32A32_SINT:
- case PIPE_FORMAT_R32A32_FLOAT:
- return V_028C70_SWAP_ALT;
- case PIPE_FORMAT_R8G8_UNORM:
- case PIPE_FORMAT_R8G8_SNORM:
- case PIPE_FORMAT_R8G8_UINT:
- case PIPE_FORMAT_R8G8_SINT:
- return V_028C70_SWAP_STD;
-
- case PIPE_FORMAT_R16_UNORM:
- case PIPE_FORMAT_R16_SNORM:
- case PIPE_FORMAT_R16_UINT:
- case PIPE_FORMAT_R16_SINT:
- case PIPE_FORMAT_R16_FLOAT:
- return V_028C70_SWAP_STD;
-
- /* 32-bit buffers. */
- case PIPE_FORMAT_A8B8G8R8_SRGB:
- return V_028C70_SWAP_STD_REV;
- case PIPE_FORMAT_B8G8R8A8_SRGB:
- return V_028C70_SWAP_ALT;
-
- case PIPE_FORMAT_B8G8R8A8_UNORM:
- case PIPE_FORMAT_B8G8R8X8_UNORM:
- return V_028C70_SWAP_ALT;
-
- case PIPE_FORMAT_A8R8G8B8_UNORM:
- case PIPE_FORMAT_X8R8G8B8_UNORM:
- return V_028C70_SWAP_ALT_REV;
- case PIPE_FORMAT_R8G8B8A8_SNORM:
- case PIPE_FORMAT_R8G8B8A8_UNORM:
- case PIPE_FORMAT_R8G8B8A8_SINT:
- case PIPE_FORMAT_R8G8B8A8_UINT:
- case PIPE_FORMAT_R8G8B8X8_UNORM:
- case PIPE_FORMAT_R8G8B8X8_SNORM:
- case PIPE_FORMAT_R8G8B8X8_SRGB:
- case PIPE_FORMAT_R8G8B8X8_UINT:
- case PIPE_FORMAT_R8G8B8X8_SINT:
- return V_028C70_SWAP_STD;
-
- case PIPE_FORMAT_A8B8G8R8_UNORM:
- case PIPE_FORMAT_X8B8G8R8_UNORM:
- /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
- return V_028C70_SWAP_STD_REV;
-
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- return V_028C70_SWAP_STD;
-
- case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- return V_028C70_SWAP_STD_REV;
-
- case PIPE_FORMAT_R10G10B10A2_UNORM:
- case PIPE_FORMAT_R10G10B10X2_SNORM:
- case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
- return V_028C70_SWAP_STD;
-
- case PIPE_FORMAT_B10G10R10A2_UNORM:
- case PIPE_FORMAT_B10G10R10A2_UINT:
- case PIPE_FORMAT_B10G10R10X2_UNORM:
- return V_028C70_SWAP_ALT;
-
- case PIPE_FORMAT_R11G11B10_FLOAT:
- case PIPE_FORMAT_R32_FLOAT:
- case PIPE_FORMAT_R32_UINT:
- case PIPE_FORMAT_R32_SINT:
- case PIPE_FORMAT_Z32_FLOAT:
- case PIPE_FORMAT_R16G16_FLOAT:
- case PIPE_FORMAT_R16G16_UNORM:
- case PIPE_FORMAT_R16G16_SNORM:
- case PIPE_FORMAT_R16G16_UINT:
- case PIPE_FORMAT_R16G16_SINT:
- return V_028C70_SWAP_STD;
-
- /* 64-bit buffers. */
- case PIPE_FORMAT_R32G32_FLOAT:
- case PIPE_FORMAT_R32G32_UINT:
- case PIPE_FORMAT_R32G32_SINT:
- case PIPE_FORMAT_R16G16B16A16_UNORM:
- case PIPE_FORMAT_R16G16B16A16_SNORM:
- case PIPE_FORMAT_R16G16B16A16_UINT:
- case PIPE_FORMAT_R16G16B16A16_SINT:
- case PIPE_FORMAT_R16G16B16A16_FLOAT:
- case PIPE_FORMAT_R16G16B16X16_UNORM:
- case PIPE_FORMAT_R16G16B16X16_SNORM:
- case PIPE_FORMAT_R16G16B16X16_FLOAT:
- case PIPE_FORMAT_R16G16B16X16_UINT:
- case PIPE_FORMAT_R16G16B16X16_SINT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
-
- /* 128-bit buffers. */
- case PIPE_FORMAT_R32G32B32A32_FLOAT:
- case PIPE_FORMAT_R32G32B32A32_SNORM:
- case PIPE_FORMAT_R32G32B32A32_UNORM:
- case PIPE_FORMAT_R32G32B32A32_SINT:
- case PIPE_FORMAT_R32G32B32A32_UINT:
- case PIPE_FORMAT_R32G32B32X32_FLOAT:
- case PIPE_FORMAT_R32G32B32X32_UINT:
- case PIPE_FORMAT_R32G32B32X32_SINT:
- return V_028C70_SWAP_STD;
- default:
- R600_ERR("unsupported colorswap format %d\n", format);
- return ~0U;
- }
- return ~0U;
-}
-
-static uint32_t r600_translate_colorformat(enum pipe_format format)
-{
- switch (format) {
- /* 8-bit buffers. */
- case PIPE_FORMAT_A8_UNORM:
- case PIPE_FORMAT_A8_SNORM:
- case PIPE_FORMAT_A8_UINT:
- case PIPE_FORMAT_A8_SINT:
- case PIPE_FORMAT_I8_UNORM:
- case PIPE_FORMAT_I8_SNORM:
- case PIPE_FORMAT_I8_UINT:
- case PIPE_FORMAT_I8_SINT:
- case PIPE_FORMAT_L8_UNORM:
- case PIPE_FORMAT_L8_SNORM:
- case PIPE_FORMAT_L8_UINT:
- case PIPE_FORMAT_L8_SINT:
- case PIPE_FORMAT_L8_SRGB:
- case PIPE_FORMAT_R8_UNORM:
- case PIPE_FORMAT_R8_SNORM:
- case PIPE_FORMAT_R8_UINT:
- case PIPE_FORMAT_R8_SINT:
- return V_028C70_COLOR_8;
-
- /* 16-bit buffers. */
- case PIPE_FORMAT_B5G6R5_UNORM:
- return V_028C70_COLOR_5_6_5;
-
- case PIPE_FORMAT_B5G5R5A1_UNORM:
- case PIPE_FORMAT_B5G5R5X1_UNORM:
- return V_028C70_COLOR_1_5_5_5;
-
- case PIPE_FORMAT_B4G4R4A4_UNORM:
- case PIPE_FORMAT_B4G4R4X4_UNORM:
- return V_028C70_COLOR_4_4_4_4;
-
- case PIPE_FORMAT_Z16_UNORM:
- return V_028C70_COLOR_16;
-
- case PIPE_FORMAT_L8A8_UNORM:
- case PIPE_FORMAT_L8A8_SNORM:
- case PIPE_FORMAT_L8A8_UINT:
- case PIPE_FORMAT_L8A8_SINT:
- case PIPE_FORMAT_L8A8_SRGB:
- case PIPE_FORMAT_R8G8_UNORM:
- case PIPE_FORMAT_R8G8_SNORM:
- case PIPE_FORMAT_R8G8_UINT:
- case PIPE_FORMAT_R8G8_SINT:
- case PIPE_FORMAT_R8A8_UNORM:
- case PIPE_FORMAT_R8A8_SNORM:
- case PIPE_FORMAT_R8A8_UINT:
- case PIPE_FORMAT_R8A8_SINT:
- return V_028C70_COLOR_8_8;
-
- case PIPE_FORMAT_R16_UNORM:
- case PIPE_FORMAT_R16_SNORM:
- case PIPE_FORMAT_R16_UINT:
- case PIPE_FORMAT_R16_SINT:
- case PIPE_FORMAT_A16_UNORM:
- case PIPE_FORMAT_A16_SNORM:
- case PIPE_FORMAT_A16_UINT:
- case PIPE_FORMAT_A16_SINT:
- case PIPE_FORMAT_L16_UNORM:
- case PIPE_FORMAT_L16_SNORM:
- case PIPE_FORMAT_L16_UINT:
- case PIPE_FORMAT_L16_SINT:
- case PIPE_FORMAT_I16_UNORM:
- case PIPE_FORMAT_I16_SNORM:
- case PIPE_FORMAT_I16_UINT:
- case PIPE_FORMAT_I16_SINT:
- return V_028C70_COLOR_16;
-
- case PIPE_FORMAT_R16_FLOAT:
- case PIPE_FORMAT_A16_FLOAT:
- case PIPE_FORMAT_L16_FLOAT:
- case PIPE_FORMAT_I16_FLOAT:
- return V_028C70_COLOR_16_FLOAT;
-
- /* 32-bit buffers. */
- case PIPE_FORMAT_A8B8G8R8_SRGB:
- case PIPE_FORMAT_A8B8G8R8_UNORM:
- case PIPE_FORMAT_A8R8G8B8_UNORM:
- case PIPE_FORMAT_B8G8R8A8_SRGB:
- case PIPE_FORMAT_B8G8R8A8_UNORM:
- case PIPE_FORMAT_B8G8R8X8_UNORM:
- case PIPE_FORMAT_R8G8B8A8_SNORM:
- case PIPE_FORMAT_R8G8B8A8_UNORM:
- case PIPE_FORMAT_R8G8B8X8_UNORM:
- case PIPE_FORMAT_R8G8B8X8_SNORM:
- case PIPE_FORMAT_R8G8B8X8_SRGB:
- case PIPE_FORMAT_R8G8B8X8_UINT:
- case PIPE_FORMAT_R8G8B8X8_SINT:
- case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
- case PIPE_FORMAT_X8B8G8R8_UNORM:
- case PIPE_FORMAT_X8R8G8B8_UNORM:
- case PIPE_FORMAT_R8G8B8_UNORM:
- case PIPE_FORMAT_R8G8B8A8_SINT:
- case PIPE_FORMAT_R8G8B8A8_UINT:
- return V_028C70_COLOR_8_8_8_8;
-
- case PIPE_FORMAT_R10G10B10A2_UNORM:
- case PIPE_FORMAT_R10G10B10X2_SNORM:
- case PIPE_FORMAT_B10G10R10A2_UNORM:
- case PIPE_FORMAT_B10G10R10A2_UINT:
- case PIPE_FORMAT_B10G10R10X2_UNORM:
- case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
- return V_028C70_COLOR_2_10_10_10;
-
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- return V_028C70_COLOR_8_24;
-
- case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- return V_028C70_COLOR_24_8;
-
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- return V_028C70_COLOR_X24_8_32_FLOAT;
-
- case PIPE_FORMAT_R32_UINT:
- case PIPE_FORMAT_R32_SINT:
- case PIPE_FORMAT_A32_UINT:
- case PIPE_FORMAT_A32_SINT:
- case PIPE_FORMAT_L32_UINT:
- case PIPE_FORMAT_L32_SINT:
- case PIPE_FORMAT_I32_UINT:
- case PIPE_FORMAT_I32_SINT:
- return V_028C70_COLOR_32;
-
- case PIPE_FORMAT_R32_FLOAT:
- case PIPE_FORMAT_A32_FLOAT:
- case PIPE_FORMAT_L32_FLOAT:
- case PIPE_FORMAT_I32_FLOAT:
- case PIPE_FORMAT_Z32_FLOAT:
- return V_028C70_COLOR_32_FLOAT;
-
- case PIPE_FORMAT_R16G16_FLOAT:
- case PIPE_FORMAT_L16A16_FLOAT:
- case PIPE_FORMAT_R16A16_FLOAT:
- return V_028C70_COLOR_16_16_FLOAT;
-
- case PIPE_FORMAT_R16G16_UNORM:
- case PIPE_FORMAT_R16G16_SNORM:
- case PIPE_FORMAT_R16G16_UINT:
- case PIPE_FORMAT_R16G16_SINT:
- case PIPE_FORMAT_L16A16_UNORM:
- case PIPE_FORMAT_L16A16_SNORM:
- case PIPE_FORMAT_L16A16_UINT:
- case PIPE_FORMAT_L16A16_SINT:
- case PIPE_FORMAT_R16A16_UNORM:
- case PIPE_FORMAT_R16A16_SNORM:
- case PIPE_FORMAT_R16A16_UINT:
- case PIPE_FORMAT_R16A16_SINT:
- return V_028C70_COLOR_16_16;
-
- case PIPE_FORMAT_R11G11B10_FLOAT:
- return V_028C70_COLOR_10_11_11_FLOAT;
-
- /* 64-bit buffers. */
- case PIPE_FORMAT_R16G16B16A16_UINT:
- case PIPE_FORMAT_R16G16B16A16_SINT:
- case PIPE_FORMAT_R16G16B16A16_UNORM:
- case PIPE_FORMAT_R16G16B16A16_SNORM:
- case PIPE_FORMAT_R16G16B16X16_UNORM:
- case PIPE_FORMAT_R16G16B16X16_SNORM:
- case PIPE_FORMAT_R16G16B16X16_UINT:
- case PIPE_FORMAT_R16G16B16X16_SINT:
- return V_028C70_COLOR_16_16_16_16;
-
- case PIPE_FORMAT_R16G16B16A16_FLOAT:
- case PIPE_FORMAT_R16G16B16X16_FLOAT:
- return V_028C70_COLOR_16_16_16_16_FLOAT;
-
- case PIPE_FORMAT_R32G32_FLOAT:
- case PIPE_FORMAT_L32A32_FLOAT:
- case PIPE_FORMAT_R32A32_FLOAT:
- return V_028C70_COLOR_32_32_FLOAT;
-
- case PIPE_FORMAT_R32G32_SINT:
- case PIPE_FORMAT_R32G32_UINT:
- case PIPE_FORMAT_L32A32_UINT:
- case PIPE_FORMAT_L32A32_SINT:
- return V_028C70_COLOR_32_32;
-
- /* 128-bit buffers. */
- case PIPE_FORMAT_R32G32B32A32_SNORM:
- case PIPE_FORMAT_R32G32B32A32_UNORM:
- case PIPE_FORMAT_R32G32B32A32_SINT:
- case PIPE_FORMAT_R32G32B32A32_UINT:
- case PIPE_FORMAT_R32G32B32X32_UINT:
- case PIPE_FORMAT_R32G32B32X32_SINT:
- return V_028C70_COLOR_32_32_32_32;
- case PIPE_FORMAT_R32G32B32A32_FLOAT:
- case PIPE_FORMAT_R32G32B32X32_FLOAT:
- return V_028C70_COLOR_32_32_32_32_FLOAT;
-
- /* YUV buffers. */
- case PIPE_FORMAT_UYVY:
- case PIPE_FORMAT_YUYV:
- default:
- return ~0U; /* Unsupported. */
- }
-}
-
-static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
-{
- if (R600_BIG_ENDIAN) {
- switch(colorformat) {
-
- /* 8-bit buffers. */
- case V_028C70_COLOR_8:
- return ENDIAN_NONE;
-
- /* 16-bit buffers. */
- case V_028C70_COLOR_5_6_5:
- case V_028C70_COLOR_1_5_5_5:
- case V_028C70_COLOR_4_4_4_4:
- case V_028C70_COLOR_16:
- case V_028C70_COLOR_8_8:
- return ENDIAN_8IN16;
-
- /* 32-bit buffers. */
- case V_028C70_COLOR_8_8_8_8:
- case V_028C70_COLOR_2_10_10_10:
- case V_028C70_COLOR_8_24:
- case V_028C70_COLOR_24_8:
- case V_028C70_COLOR_32_FLOAT:
- case V_028C70_COLOR_16_16_FLOAT:
- case V_028C70_COLOR_16_16:
- return ENDIAN_8IN32;
-
- /* 64-bit buffers. */
- case V_028C70_COLOR_16_16_16_16:
- case V_028C70_COLOR_16_16_16_16_FLOAT:
- return ENDIAN_8IN16;
-
- case V_028C70_COLOR_32_32_FLOAT:
- case V_028C70_COLOR_32_32:
- case V_028C70_COLOR_X24_8_32_FLOAT:
- return ENDIAN_8IN32;
-
- /* 96-bit buffers. */
- case V_028C70_COLOR_32_32_32_FLOAT:
- /* 128-bit buffers. */
- case V_028C70_COLOR_32_32_32_32_FLOAT:
- case V_028C70_COLOR_32_32_32_32:
- return ENDIAN_8IN32;
- default:
- return ENDIAN_NONE; /* Unsupported. */
- }
- } else {
- return ENDIAN_NONE;
- }
-}
-
static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
{
return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
}
-static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
+static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
{
- return r600_translate_colorformat(format) != ~0U &&
+ return r600_translate_colorformat(chip, format) != ~0U &&
r600_translate_colorswap(format) != ~0U;
}
return r600_translate_dbformat(format) != ~0U;
}
+static inline bool r600_is_blending_supported(enum pipe_format format)
+{
+ return !(util_format_is_pure_integer(format) || util_format_is_depth_or_stencil(format));
+}
+
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
}
}
- if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
- r600_is_sampler_format_supported(screen, format)) {
- retval |= PIPE_BIND_SAMPLER_VIEW;
+ if (usage & PIPE_BIND_SAMPLER_VIEW) {
+ if (target == PIPE_BUFFER) {
+ if (r600_is_vertex_format_supported(format))
+ retval |= PIPE_BIND_SAMPLER_VIEW;
+ } else {
+ if (r600_is_sampler_format_supported(screen, format))
+ retval |= PIPE_BIND_SAMPLER_VIEW;
+ }
}
if ((usage & (PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
PIPE_BIND_SHARED)) &&
- r600_is_colorbuffer_format_supported(format)) {
+ r600_is_colorbuffer_format_supported(rscreen->b.chip_class, format)) {
retval |= usage &
(PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |
if (usage & PIPE_BIND_TRANSFER_WRITE)
retval |= PIPE_BIND_TRANSFER_WRITE;
+ if ((usage & PIPE_BIND_BLENDABLE) &&
+ r600_is_blending_supported(format))
+ retval |= PIPE_BIND_BLENDABLE;
+
return retval == usage;
}
S_028810_PS_UCP_MODE(3) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
- S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
+ S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
+ S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
rs->multisample_enable = state->multisample;
/* offset */
S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
- if (rctx->chip_class == CAYMAN) {
+ if (rctx->b.chip_class == CAYMAN) {
r600_store_context_reg(&rs->buffer, CM_R_028BE4_PA_SU_VTX_CNTL,
S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
state->fill_back != PIPE_POLYGON_MODE_FILL) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
- r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
return rs;
}
evergreen_create_sampler_view_custom(struct pipe_context *ctx,
struct pipe_resource *texture,
const struct pipe_sampler_view *state,
- unsigned width0, unsigned height0)
+ unsigned width0, unsigned height0,
+ unsigned force_level)
{
struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
enum pipe_format pipe_format = state->format;
struct radeon_surface_level *surflevel;
+ unsigned base_level, first_level, last_level;
+ uint64_t va;
if (view == NULL)
return NULL;
endian = r600_colorformat_endian_swap(format);
+ base_level = 0;
+ first_level = state->u.tex.first_level;
+ last_level = state->u.tex.last_level;
width = width0;
height = height0;
depth = texture->depth0;
- pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
+
+ if (force_level) {
+ base_level = force_level;
+ first_level = 0;
+ last_level = 0;
+ width = u_minify(width, force_level);
+ height = u_minify(height, force_level);
+ depth = u_minify(depth, force_level);
+ }
+
+ pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
non_disp_tiling = tmp->non_disp_tiling;
- switch (surflevel[0].mode) {
+ switch (surflevel[base_level].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
break;
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
- fmask_bankh = eg_bank_wh(tmp->fmask_bank_height);
+ fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
/* 128 bit formats require tile type = 1 */
- if (rscreen->chip_class == CAYMAN) {
+ if (rscreen->b.chip_class == CAYMAN) {
if (util_format_get_blocksize(pipe_format) >= 16)
non_disp_tiling = 1;
}
- nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
+ nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
} else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
depth = texture->array_size / 6;
+ va = r600_resource_va(ctx->screen, texture);
+
view->tex_resource = &tmp->resource;
view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
S_030000_PITCH((pitch / 8) - 1) |
S_030000_TEX_WIDTH(width - 1));
- if (rscreen->chip_class == CAYMAN)
+ if (rscreen->b.chip_class == CAYMAN)
view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
else
view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(non_disp_tiling);
view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- view->tex_resource_words[2] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
/* TEX_RESOURCE_WORD3.MIP_ADDRESS */
if (texture->nr_samples > 1 && rscreen->has_compressed_msaa_texturing) {
view->skip_mip_address_reloc = true;
} else {
/* FMASK should be in MIP_ADDRESS for multisample textures */
- view->tex_resource_words[3] = (tmp->fmask_offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
}
- } else if (state->u.tex.last_level && texture->nr_samples <= 1) {
- view->tex_resource_words[3] = (surflevel[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ } else if (last_level && texture->nr_samples <= 1) {
+ view->tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
} else {
- view->tex_resource_words[3] = (surflevel[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
+ view->tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
}
view->tex_resource_words[4] = (word4 |
if (texture->nr_samples > 1) {
unsigned log_samples = util_logbase2(texture->nr_samples);
- if (rscreen->chip_class == CAYMAN) {
+ if (rscreen->b.chip_class == CAYMAN) {
view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
}
/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh);
} else {
- view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
- view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
+ view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level);
+ view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level);
/* aniso max 16 samples */
view->tex_resource_words[6] |= S_030018_MAX_ANISO(4);
}
const struct pipe_sampler_view *state)
{
return evergreen_create_sampler_view_custom(ctx, tex, state,
- tex->width0, tex->height0);
+ tex->width0, tex->height0, 0);
}
static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct pipe_clip_state *state = &rctx->clip_state.state;
r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
- r600_write_array(cs, 6*4, (unsigned*)state);
+ radeon_emit_array(cs, (unsigned*)state, 6*4);
}
static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
tl_y = 1;
/* cayman hw workaround */
- if (rctx->chip_class == CAYMAN) {
+ if (rctx->b.chip_class == CAYMAN) {
if (br_x == 1 && br_y == 1)
br_x = 2;
}
const struct pipe_scissor_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
+ int i;
- rctx->scissor.scissor = *state;
- rctx->scissor.atom.dirty = true;
+ for (i = start_slot; i < start_slot + num_scissors; i++) {
+ rctx->scissor[i].scissor = state[i - start_slot];
+ rctx->scissor[i].atom.dirty = true;
+ }
}
static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
- struct pipe_scissor_state *state = &rctx->scissor.scissor;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct r600_scissor_state *rstate = (struct r600_scissor_state *)atom;
+ struct pipe_scissor_state *state = &rstate->scissor;
+ unsigned offset = rstate->idx * 4 * 2;
uint32_t tl, br;
evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
- r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
- r600_write_value(cs, tl);
- r600_write_value(cs, br);
+ r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2);
+ radeon_emit(cs, tl);
+ radeon_emit(cs, br);
}
/**
struct r600_surface *surf)
{
struct pipe_resource *pipe_buffer = surf->base.texture;
- unsigned format = r600_translate_colorformat(surf->base.format);
+ unsigned format = r600_translate_colorformat(rctx->b.chip_class,
+ surf->base.format);
unsigned endian = r600_colorformat_endian_swap(format);
unsigned swap = r600_translate_colorswap(surf->base.format);
unsigned block_size =
align(util_format_get_blocksize(pipe_buffer->format), 4);
unsigned pitch_alignment =
- MAX2(64, rctx->screen->tiling_info.group_bytes / block_size);
+ MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
/* XXX: This is copied from evergreen_init_color_surface(). I don't
}
surf->cb_color_base =
- r600_resource_va(rctx->context.screen, pipe_buffer) >> 8;
+ r600_resource_va(rctx->b.b.screen, pipe_buffer) >> 8;
surf->cb_color_pitch = (pitch / 8) - 1;
util_range_add(&r600_resource(pipe_buffer)->valid_buffer_range,
0, pipe_buffer->width0);
- surf->cb_color_cmask = surf->cb_color_base;
- surf->cb_color_cmask_slice = 0;
surf->cb_color_fmask = surf->cb_color_base;
surf->cb_color_fmask_slice = 0;
}
struct pipe_resource *pipe_tex = surf->base.texture;
unsigned level = surf->base.u.tex.level;
unsigned pitch, slice;
- unsigned color_info, color_attrib, color_dim = 0;
+ unsigned color_info, color_attrib, color_dim = 0, color_view;
unsigned format, swap, ntype, endian;
uint64_t offset, base_offset;
unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
bool blend_clamp = 0, blend_bypass = 0;
offset = rtex->surface.level[level].offset;
- if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+ if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
+ assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
offset += rtex->surface.level[level].slice_size *
surf->base.u.tex.first_layer;
- }
+ color_view = 0;
+ } else
+ color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
+ S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
+
pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
if (slice) {
macro_aspect = rtex->surface.mtilea;
bankw = rtex->surface.bankw;
bankh = rtex->surface.bankh;
- fmask_bankh = rtex->fmask_bank_height;
+ fmask_bankh = rtex->fmask.bank_height;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
fmask_bankh = eg_bank_wh(fmask_bankh);
/* 128 bit formats require tile type = 1 */
- if (rscreen->chip_class == CAYMAN) {
+ if (rscreen->b.chip_class == CAYMAN) {
if (util_format_get_blocksize(surf->base.format) >= 16)
non_disp_tiling = 1;
}
- nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
+ nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
desc = util_format_description(surf->base.format);
for (i = 0; i < 4; i++) {
if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
S_028C74_NON_DISP_TILING_ORDER(non_disp_tiling) |
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
- if (rctx->chip_class == CAYMAN) {
+ if (rctx->b.chip_class == CAYMAN) {
color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] ==
UTIL_FORMAT_SWIZZLE_1);
ntype = V_028C70_NUMBER_UINT;
}
- format = r600_translate_colorformat(surf->base.format);
+ format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
assert(format != ~0);
swap = r600_translate_colorswap(surf->base.format);
S_028C70_NUMBER_TYPE(ntype) |
S_028C70_ENDIAN(endian);
- if (rtex->is_rat) {
- color_info |= S_028C70_RAT(1);
- color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0 & 0xffff)
- | S_028C78_HEIGHT_MAX((pipe_tex->width0 >> 16) & 0xffff);
- }
-
/* EXPORT_NORM is an optimzation that can be enabled for better
* performance in certain cases.
* EXPORT_NORM can be enabled if:
surf->export_16bpc = true;
}
- if (rtex->fmask_size && rtex->cmask_size) {
- color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
+ if (rtex->fmask.size) {
+ color_info |= S_028C70_COMPRESSION(1);
}
- base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
+ base_offset = r600_resource_va(rctx->b.b.screen, pipe_tex);
/* XXX handle enabling of CB beyond BASE8 which has different offset */
surf->cb_color_base = (base_offset + offset) >> 8;
surf->cb_color_info = color_info;
surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
- if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
- surf->cb_color_view = 0;
- } else {
- surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
- S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
- }
+ surf->cb_color_view = color_view;
surf->cb_color_attrib = color_attrib;
- if (rtex->fmask_size && rtex->cmask_size) {
- surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
- surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
+ if (rtex->fmask.size) {
+ surf->cb_color_fmask = (base_offset + rtex->fmask.offset) >> 8;
} else {
surf->cb_color_fmask = surf->cb_color_base;
- surf->cb_color_cmask = surf->cb_color_base;
}
- surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask_slice_tile_max);
- surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
+ surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
surf->color_initialized = true;
}
struct r600_surface *surf)
{
struct r600_screen *rscreen = rctx->screen;
- struct pipe_screen *screen = &rscreen->screen;
+ struct pipe_screen *screen = &rscreen->b.b;
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
uint64_t offset;
unsigned level, pitch, slice, format, array_mode;
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
- nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
+ nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
offset >>= 8;
- surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
- S_028040_FORMAT(format) |
- S_028040_TILE_SPLIT(tile_split)|
- S_028040_NUM_BANKS(nbanks) |
- S_028040_BANK_WIDTH(bankw) |
- S_028040_BANK_HEIGHT(bankh) |
- S_028040_MACRO_TILE_ASPECT(macro_aspect);
- if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
- surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
+ surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
+ S_028040_FORMAT(format) |
+ S_028040_TILE_SPLIT(tile_split)|
+ S_028040_NUM_BANKS(nbanks) |
+ S_028040_BANK_WIDTH(bankw) |
+ S_028040_BANK_HEIGHT(bankh) |
+ S_028040_MACRO_TILE_ASPECT(macro_aspect);
+ if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
+ surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
}
surf->db_depth_base = offset;
surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
surf->db_stencil_base = offset;
/* DRM 2.6.18 allows the INVALID format to disable stencil.
* Older kernels are out of luck. */
- surf->db_stencil_info = rctx->screen->info.drm_minor >= 18 ?
+ surf->db_stencil_info = rctx->screen->b.info.drm_minor >= 18 ?
S_028044_FORMAT(V_028044_STENCIL_INVALID) :
S_028044_FORMAT(V_028044_STENCIL_8);
}
- surf->htile_enabled = 0;
/* use htile only for first level */
- if (rtex->htile && !level) {
- uint64_t va = r600_resource_va(&rctx->screen->screen, &rtex->htile->b.b);
- surf->htile_enabled = 1;
+ if (rtex->htile_buffer && !level) {
+ uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
S_028ABC_HTILE_HEIGHT(1) |
S_028ABC_FULL_CACHE(1) |
S_028ABC_LINEAR(1);
- surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
+ surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
surf->db_preload_control = 0;
}
uint32_t i, log_samples;
if (rctx->framebuffer.state.nr_cbufs) {
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
-
- if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
- rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
- }
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+ rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
+ R600_CONTEXT_FLUSH_AND_INV_CB_META;
}
if (rctx->framebuffer.state.zsbuf) {
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+ rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
- if (rtex->htile) {
- rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
+ if (rtex->htile_buffer) {
+ rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META;
}
}
/* Colorbuffers. */
rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
- rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
+ rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
util_format_is_pure_integer(state->cbufs[0]->format);
rctx->framebuffer.compressed_cb_mask = 0;
-
- if (state->nr_cbufs)
- rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
- else if (state->zsbuf)
- rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
- else
- rctx->framebuffer.nr_samples = 0;
+ rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
for (i = 0; i < state->nr_cbufs; i++) {
surf = (struct r600_surface*)state->cbufs[i];
+ if (!surf)
+ continue;
+
rtex = (struct r600_texture*)surf->base.texture;
r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
rctx->framebuffer.export_16bpc = false;
}
- if (rtex->fmask_size && rtex->cmask_size) {
+ if (rtex->fmask.size && rtex->cmask.size) {
rctx->framebuffer.compressed_cb_mask |= 1 << i;
}
}
/* Update alpha-test state dependencies.
* Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
+ bool alphatest_bypass = false;
+ bool export_16bpc = true;
+
surf = (struct r600_surface*)state->cbufs[0];
- if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
- rctx->alphatest_state.bypass = surf->alphatest_bypass;
+ if (surf) {
+ alphatest_bypass = surf->alphatest_bypass;
+ export_16bpc = surf->export_16bpc;
+ }
+
+ if (rctx->alphatest_state.bypass != alphatest_bypass) {
+ rctx->alphatest_state.bypass = alphatest_bypass;
rctx->alphatest_state.atom.dirty = true;
}
- if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
- rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
+ if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
+ rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
rctx->alphatest_state.atom.dirty = true;
}
}
}
log_samples = util_logbase2(rctx->framebuffer.nr_samples);
- if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
+ /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */
+ if ((rctx->b.chip_class == CAYMAN ||
+ rctx->b.family == CHIP_RV770) &&
+ rctx->db_misc_state.log_samples != log_samples) {
rctx->db_misc_state.log_samples = log_samples;
rctx->db_misc_state.atom.dirty = true;
}
- evergreen_update_db_shader_control(rctx);
/* Calculate the CS size. */
rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
/* MSAA. */
- if (rctx->chip_class == EVERGREEN) {
- switch (rctx->framebuffer.nr_samples) {
- case 2:
- case 4:
- rctx->framebuffer.atom.num_dw += 6;
- break;
- case 8:
- rctx->framebuffer.atom.num_dw += 10;
- break;
- }
- rctx->framebuffer.atom.num_dw += 4;
- } else {
- switch (rctx->framebuffer.nr_samples) {
- case 2:
- case 4:
- rctx->framebuffer.atom.num_dw += 12;
- break;
- case 8:
- rctx->framebuffer.atom.num_dw += 16;
- break;
- case 16:
- rctx->framebuffer.atom.num_dw += 18;
- break;
- }
- rctx->framebuffer.atom.num_dw += 7;
- }
+ if (rctx->b.chip_class == EVERGREEN)
+ rctx->framebuffer.atom.num_dw += 14; /* Evergreen */
+ else
+ rctx->framebuffer.atom.num_dw += 25; /* Cayman */
/* Colorbuffers. */
- rctx->framebuffer.atom.num_dw += state->nr_cbufs * 21;
+ rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
if (rctx->keep_tiling_flags)
rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
rctx->framebuffer.atom.num_dw += 24;
if (rctx->keep_tiling_flags)
rctx->framebuffer.atom.num_dw += 2;
- } else if (rctx->screen->info.drm_minor >= 18) {
+ } else if (rctx->screen->b.info.drm_minor >= 18) {
rctx->framebuffer.atom.num_dw += 4;
}
rctx->framebuffer.atom.dirty = true;
}
-#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
- (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
- (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
- (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
- (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
-/* 2xMSAA
- * There are two locations (-4, 4), (4, -4). */
-static uint32_t sample_locs_2x[] = {
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
-};
-static unsigned max_dist_2x = 4;
-/* 4xMSAA
- * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
-static uint32_t sample_locs_4x[] = {
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
-};
-static unsigned max_dist_4x = 6;
/* 8xMSAA */
static uint32_t sample_locs_8x[] = {
FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
break;
case 2:
offset = 4 * (sample_index * 2);
- val.idx = (sample_locs_2x[0] >> offset) & 0xf;
+ val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
+ val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
out_value[1] = (float)(val.idx + 8) / 16.0f;
break;
case 4:
offset = 4 * (sample_index * 2);
- val.idx = (sample_locs_4x[0] >> offset) & 0xf;
+ val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
+ val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
out_value[1] = (float)(val.idx + 8) / 16.0f;
break;
case 8:
static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
unsigned max_dist = 0;
switch (nr_samples) {
nr_samples = 0;
break;
case 2:
- r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_2x));
- r600_write_array(cs, Elements(sample_locs_2x), sample_locs_2x);
- max_dist = max_dist_2x;
+ r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x));
+ radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x));
+ max_dist = eg_max_dist_2x;
break;
case 4:
- r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_4x));
- r600_write_array(cs, Elements(sample_locs_4x), sample_locs_4x);
- max_dist = max_dist_4x;
+ r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x));
+ radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x));
+ max_dist = eg_max_dist_4x;
break;
case 8:
r600_write_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x));
- r600_write_array(cs, Elements(sample_locs_8x), sample_locs_8x);
+ radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x));
max_dist = max_dist_8x;
break;
}
if (nr_samples > 1) {
r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
- r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
+ radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
- r600_write_value(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
+ radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
} else {
r600_write_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
- r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
- r600_write_value(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
- }
-}
-
-/* Cayman 8xMSAA */
-static uint32_t cm_sample_locs_8x[] = {
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
-};
-static unsigned cm_max_dist_8x = 8;
-/* Cayman 16xMSAA */
-static uint32_t cm_sample_locs_16x[] = {
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
-};
-static unsigned cm_max_dist_16x = 8;
-static void cayman_get_sample_position(struct pipe_context *ctx,
- unsigned sample_count,
- unsigned sample_index,
- float *out_value)
-{
- int offset, index;
- struct {
- int idx:4;
- } val;
- switch (sample_count) {
- case 1:
- default:
- out_value[0] = out_value[1] = 0.5;
- break;
- case 2:
- offset = 4 * (sample_index * 2);
- val.idx = (sample_locs_2x[0] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
- break;
- case 4:
- offset = 4 * (sample_index * 2);
- val.idx = (sample_locs_4x[0] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
- break;
- case 8:
- offset = 4 * (sample_index % 4 * 2);
- index = (sample_index / 4) * 4;
- val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
- break;
- case 16:
- offset = 4 * (sample_index % 4 * 2);
- index = (sample_index / 4) * 4;
- val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
- break;
- }
-}
-
-static void cayman_emit_msaa_state(struct r600_context *rctx, int nr_samples)
-{
-
-
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
- unsigned max_dist = 0;
-
- switch (nr_samples) {
- default:
- nr_samples = 0;
- break;
- case 2:
- r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
- r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
- r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
- r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
- max_dist = max_dist_2x;
- break;
- case 4:
- r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
- r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
- r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
- r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
- max_dist = max_dist_4x;
- break;
- case 8:
- r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
- r600_write_value(cs, cm_sample_locs_8x[0]);
- r600_write_value(cs, cm_sample_locs_8x[4]);
- r600_write_value(cs, 0);
- r600_write_value(cs, 0);
- r600_write_value(cs, cm_sample_locs_8x[1]);
- r600_write_value(cs, cm_sample_locs_8x[5]);
- r600_write_value(cs, 0);
- r600_write_value(cs, 0);
- r600_write_value(cs, cm_sample_locs_8x[2]);
- r600_write_value(cs, cm_sample_locs_8x[6]);
- r600_write_value(cs, 0);
- r600_write_value(cs, 0);
- r600_write_value(cs, cm_sample_locs_8x[3]);
- r600_write_value(cs, cm_sample_locs_8x[7]);
- max_dist = cm_max_dist_8x;
- break;
- case 16:
- r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
- r600_write_value(cs, cm_sample_locs_16x[0]);
- r600_write_value(cs, cm_sample_locs_16x[4]);
- r600_write_value(cs, cm_sample_locs_16x[8]);
- r600_write_value(cs, cm_sample_locs_16x[12]);
- r600_write_value(cs, cm_sample_locs_16x[1]);
- r600_write_value(cs, cm_sample_locs_16x[5]);
- r600_write_value(cs, cm_sample_locs_16x[9]);
- r600_write_value(cs, cm_sample_locs_16x[13]);
- r600_write_value(cs, cm_sample_locs_16x[2]);
- r600_write_value(cs, cm_sample_locs_16x[6]);
- r600_write_value(cs, cm_sample_locs_16x[10]);
- r600_write_value(cs, cm_sample_locs_16x[14]);
- r600_write_value(cs, cm_sample_locs_16x[3]);
- r600_write_value(cs, cm_sample_locs_16x[7]);
- r600_write_value(cs, cm_sample_locs_16x[11]);
- r600_write_value(cs, cm_sample_locs_16x[15]);
- max_dist = cm_max_dist_16x;
- break;
- }
-
- if (nr_samples > 1) {
- unsigned log_samples = util_logbase2(nr_samples);
-
- r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
- r600_write_value(cs, S_028C00_LAST_PIXEL(1) |
- S_028C00_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
- r600_write_value(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
- S_028BE0_MAX_SAMPLE_DIST(max_dist) |
- S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
-
- r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
- S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
- S_028804_PS_ITER_SAMPLES(log_samples) |
- S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
- S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
- S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
- S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
- } else {
- r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
- r600_write_value(cs, S_028C00_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
- r600_write_value(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
-
- r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
- S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
- S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
+ radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
+ radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
}
}
static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
unsigned nr_cbufs = state->nr_cbufs;
unsigned i, tl, br;
+ struct r600_texture *tex = NULL;
+ struct r600_surface *cb = NULL;
/* XXX support more colorbuffers once we need them */
assert(nr_cbufs <= 8);
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
- struct r600_surface *cb = (struct r600_surface*)state->cbufs[i];
- unsigned reloc = r600_context_bo_reloc(rctx,
- &rctx->rings.gfx,
- (struct r600_resource*)cb->base.texture,
- RADEON_USAGE_READWRITE);
-
- r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 11);
- r600_write_value(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
- r600_write_value(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
- r600_write_value(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
- r600_write_value(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
- r600_write_value(cs, cb->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
- r600_write_value(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
- r600_write_value(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
- r600_write_value(cs, cb->cb_color_cmask); /* R_028C7C_CB_COLOR0_CMASK */
- r600_write_value(cs, cb->cb_color_cmask_slice); /* R_028C80_CB_COLOR0_CMASK_SLICE */
- r600_write_value(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
- r600_write_value(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
-
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
- r600_write_value(cs, reloc);
+ unsigned reloc, cmask_reloc;
+
+ cb = (struct r600_surface*)state->cbufs[i];
+ if (!cb) {
+ r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
+ S_028C70_FORMAT(V_028C70_COLOR_INVALID));
+ continue;
+ }
+
+ tex = (struct r600_texture *)cb->base.texture;
+ reloc = r600_context_bo_reloc(&rctx->b,
+ &rctx->b.rings.gfx,
+ (struct r600_resource*)cb->base.texture,
+ RADEON_USAGE_READWRITE,
+ tex->surface.nsamples > 1 ?
+ RADEON_PRIO_COLOR_BUFFER_MSAA :
+ RADEON_PRIO_COLOR_BUFFER);
+
+ if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
+ cmask_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ tex->cmask_buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_COLOR_META);
+ } else {
+ cmask_reloc = reloc;
+ }
+
+ r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
+ radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
+ radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
+ radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
+ radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
+ radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
+ radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
+ radeon_emit(cs, cb->cb_color_dim); /* R_028C78_CB_COLOR0_DIM */
+ radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
+ radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
+ radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
+ radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
+ radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
+ radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
+
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */
+ radeon_emit(cs, reloc);
if (!rctx->keep_tiling_flags) {
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
+ radeon_emit(cs, reloc);
}
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */
+ radeon_emit(cs, reloc);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C7C_CB_COLOR0_CMASK */
+ radeon_emit(cs, cmask_reloc);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C84_CB_COLOR0_FMASK */
+ radeon_emit(cs, reloc);
}
/* set CB_COLOR1_INFO for possible dual-src blending */
- if (i == 1 && !((struct r600_texture*)state->cbufs[0]->texture)->is_rat) {
+ if (i == 1 && state->cbufs[0]) {
r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
- ((struct r600_surface*)state->cbufs[0])->cb_color_info);
+ cb->cb_color_info | tex->cb_color_info);
if (!rctx->keep_tiling_flags) {
- unsigned reloc = r600_context_bo_reloc(rctx,
- &rctx->rings.gfx,
+ unsigned reloc = r600_context_bo_reloc(&rctx->b,
+ &rctx->b.rings.gfx,
(struct r600_resource*)state->cbufs[0]->texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_COLOR_BUFFER);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */
+ radeon_emit(cs, reloc);
}
i++;
}
/* ZS buffer. */
if (state->zsbuf) {
struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
- unsigned reloc = r600_context_bo_reloc(rctx,
- &rctx->rings.gfx,
+ unsigned reloc = r600_context_bo_reloc(&rctx->b,
+ &rctx->b.rings.gfx,
(struct r600_resource*)state->zsbuf->texture,
- RADEON_USAGE_READWRITE);
+ RADEON_USAGE_READWRITE,
+ zb->base.texture->nr_samples > 1 ?
+ RADEON_PRIO_DEPTH_BUFFER_MSAA :
+ RADEON_PRIO_DEPTH_BUFFER);
r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
zb->pa_su_poly_offset_db_fmt_cntl);
r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
- r600_write_value(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
- r600_write_value(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
- r600_write_value(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
- r600_write_value(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
- r600_write_value(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
- r600_write_value(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
- r600_write_value(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
- r600_write_value(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
+ radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
+ radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
+ radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
+ radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
+ radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
+ radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
+ radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
+ radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
if (!rctx->keep_tiling_flags) {
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */
+ radeon_emit(cs, reloc);
}
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */
+ radeon_emit(cs, reloc);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_02804C_DB_STENCIL_READ_BASE */
+ radeon_emit(cs, reloc);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028050_DB_Z_WRITE_BASE */
+ radeon_emit(cs, reloc);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
- r600_write_value(cs, reloc);
- } else if (rctx->screen->info.drm_minor >= 18) {
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028054_DB_STENCIL_WRITE_BASE */
+ radeon_emit(cs, reloc);
+ } else if (rctx->screen->b.info.drm_minor >= 18) {
/* DRM 2.6.18 allows the INVALID format to disable depth/stencil.
* Older kernels are out of luck. */
r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
- r600_write_value(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
- r600_write_value(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
+ radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
+ radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
}
/* Framebuffer dimensions. */
evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
r600_write_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
- r600_write_value(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
- r600_write_value(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
+ radeon_emit(cs, tl); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
+ radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
- if (rctx->chip_class == EVERGREEN) {
+ if (rctx->b.chip_class == EVERGREEN) {
evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
} else {
- cayman_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
+ cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples);
}
}
static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
float offset_units = state->offset_units;
float offset_scale = state->offset_scale;
}
r600_write_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
- r600_write_value(cs, fui(offset_scale));
- r600_write_value(cs, fui(offset_units));
- r600_write_value(cs, fui(offset_scale));
- r600_write_value(cs, fui(offset_units));
+ radeon_emit(cs, fui(offset_scale));
+ radeon_emit(cs, fui(offset_units));
+ radeon_emit(cs, fui(offset_scale));
+ radeon_emit(cs, fui(offset_units));
}
static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
- r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
+ radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
/* Always enable the first colorbuffer in CB_SHADER_MASK. This
* will assure that the alpha-test will work even if there is
* no colorbuffer bound. */
- r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
+ radeon_emit(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
}
static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_db_state *a = (struct r600_db_state*)atom;
- if (a->rsurf && a->rsurf->htile_enabled) {
+ if (a->rsurf && a->rsurf->db_htile_surface) {
struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
unsigned reloc_idx;
- r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear));
+ r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
r600_write_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control);
r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
- reloc_idx = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rtex->htile, RADEON_USAGE_READWRITE);
+ reloc_idx = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rtex->htile_buffer,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_DEPTH_META);
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] = reloc_idx;
} else {
static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
unsigned db_render_control = 0;
unsigned db_count_control = 0;
if (a->occlusion_query_enabled) {
db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
- if (rctx->chip_class == CAYMAN) {
+ if (rctx->b.chip_class == CAYMAN) {
db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
}
db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
*
* Disable hyperz for now if not writing to zbuffer.
*/
- if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled && rctx->zwritemask) {
+ if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are enabled at
}
r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
- r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
- r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
+ radeon_emit(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
+ radeon_emit(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
}
unsigned resource_offset,
unsigned pkt_flags)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
while (dirty_mask) {
rbuffer = (struct r600_resource*)vb->buffer;
assert(rbuffer);
- va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
+ va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
va += vb->buffer_offset;
/* fetch resources start at index 992 */
- r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
- r600_write_value(cs, (resource_offset + buffer_index) * 8);
- r600_write_value(cs, va); /* RESOURCEi_WORD0 */
- r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
- r600_write_value(cs, /* RESOURCEi_WORD2 */
+ radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
+ radeon_emit(cs, (resource_offset + buffer_index) * 8);
+ radeon_emit(cs, va); /* RESOURCEi_WORD0 */
+ radeon_emit(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+ radeon_emit(cs, /* RESOURCEi_WORD2 */
S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
S_030008_STRIDE(vb->stride) |
S_030008_BASE_ADDRESS_HI(va >> 32UL));
- r600_write_value(cs, /* RESOURCEi_WORD3 */
+ radeon_emit(cs, /* RESOURCEi_WORD3 */
S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
- r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
- r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
- r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
- r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
+ radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
+ radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
+ radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
+ radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD7 */
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
}
state->dirty_mask = 0;
}
unsigned reg_alu_const_cache,
unsigned pkt_flags)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
while (dirty_mask) {
struct r600_resource *rbuffer;
uint64_t va;
unsigned buffer_index = ffs(dirty_mask) - 1;
+ unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
cb = &state->cb[buffer_index];
rbuffer = (struct r600_resource*)cb->buffer;
assert(rbuffer);
- va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
+ va = r600_resource_va(&rctx->screen->b.b, &rbuffer->b.b);
va += cb->buffer_offset;
- r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
- ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
- r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
- pkt_flags);
-
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
+ if (!gs_ring_buffer) {
+ r600_write_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
+ ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
+ r600_write_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
+ pkt_flags);
+ }
- r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
- r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
- r600_write_value(cs, va); /* RESOURCEi_WORD0 */
- r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
- r600_write_value(cs, /* RESOURCEi_WORD2 */
- S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
- S_030008_STRIDE(16) |
- S_030008_BASE_ADDRESS_HI(va >> 32UL));
- r600_write_value(cs, /* RESOURCEi_WORD3 */
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
+
+ radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
+ radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
+ radeon_emit(cs, va); /* RESOURCEi_WORD0 */
+ radeon_emit(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
+ radeon_emit(cs, /* RESOURCEi_WORD2 */
+ S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
+ S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
+ S_030008_BASE_ADDRESS_HI(va >> 32UL) |
+ S_030008_DATA_FORMAT(FMT_32_32_32_32_FLOAT));
+ radeon_emit(cs, /* RESOURCEi_WORD3 */
+ S_03000C_UNCACHED(gs_ring_buffer ? 1 : 0) |
S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
- r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
- r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
- r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
- r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
+ radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
+ radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
+ radeon_emit(cs, 0); /* RESOURCEi_WORD6 */
+ radeon_emit(cs, /* RESOURCEi_WORD7 */
+ S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER));
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
- r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, rbuffer, RADEON_USAGE_READ));
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_BUFFER_RO));
dirty_mask &= ~(1 << buffer_index);
}
struct r600_samplerview_state *state,
unsigned resource_id_base)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
while (dirty_mask) {
rview = state->views[resource_index];
assert(rview);
- r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
- r600_write_value(cs, (resource_id_base + resource_index) * 8);
- r600_write_array(cs, 8, rview->tex_resource_words);
+ radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
+ radeon_emit(cs, (resource_id_base + resource_index) * 8);
+ radeon_emit_array(cs, rview->tex_resource_words, 8);
- reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rview->tex_resource,
- RADEON_USAGE_READ);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, reloc);
+ reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rview->tex_resource,
+ RADEON_USAGE_READ,
+ rview->tex_resource->b.b.nr_samples > 1 ?
+ RADEON_PRIO_SHADER_TEXTURE_MSAA :
+ RADEON_PRIO_SHADER_TEXTURE_RO);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc);
if (!rview->skip_mip_address_reloc) {
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, reloc);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc);
}
}
state->dirty_mask = 0;
unsigned resource_id_base,
unsigned border_index_reg)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint32_t dirty_mask = texinfo->states.dirty_mask;
while (dirty_mask) {
rstate = texinfo->states.states[i];
assert(rstate);
- r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
- r600_write_value(cs, (resource_id_base + i) * 3);
- r600_write_array(cs, 3, rstate->tex_sampler_words);
+ radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
+ radeon_emit(cs, (resource_id_base + i) * 3);
+ radeon_emit_array(cs, rstate->tex_sampler_words, 3);
if (rstate->border_color_use) {
r600_write_config_reg_seq(cs, border_index_reg, 5);
- r600_write_value(cs, i);
- r600_write_array(cs, 4, rstate->border_color.ui);
+ radeon_emit(cs, i);
+ radeon_emit_array(cs, rstate->border_color.ui, 4);
}
}
texinfo->states.dirty_mask = 0;
struct r600_sample_mask *s = (struct r600_sample_mask*)a;
uint8_t mask = s->sample_mask;
- r600_write_context_reg(rctx->rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
+ r600_write_context_reg(rctx->b.rings.gfx.cs, R_028C3C_PA_SC_AA_MASK,
mask | (mask << 8) | (mask << 16) | (mask << 24));
}
static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
{
struct r600_sample_mask *s = (struct r600_sample_mask*)a;
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint16_t mask = s->sample_mask;
r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
- r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
- r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
+ radeon_emit(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
+ radeon_emit(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
}
static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_cso_state *state = (struct r600_cso_state*)a;
struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
r600_write_context_reg(cs, R_0288A4_SQ_PGM_START_FS,
- (r600_resource_va(rctx->context.screen, &shader->buffer->b.b) + shader->offset) >> 8);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->buffer, RADEON_USAGE_READ));
+ (r600_resource_va(rctx->b.b.screen, &shader->buffer->b.b) + shader->offset) >> 8);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
+}
+
+static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
+{
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
+
+ uint32_t v = 0, v2 = 0, primid = 0;
+
+ if (state->geom_enable) {
+ uint32_t cut_val;
+
+ if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 128)
+ cut_val = V_028A40_GS_CUT_128;
+ else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 256)
+ cut_val = V_028A40_GS_CUT_256;
+ else if (rctx->gs_shader->current->shader.gs_max_out_vertices <= 512)
+ cut_val = V_028A40_GS_CUT_512;
+ else
+ cut_val = V_028A40_GS_CUT_1024;
+ v = S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
+ S_028B54_GS_EN(1) |
+ S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
+
+ v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
+ S_028A40_CUT_MODE(cut_val);
+
+ if (rctx->gs_shader->current->shader.gs_prim_id_input)
+ primid = 1;
+ }
+
+ r600_write_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v);
+ r600_write_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
+ r600_write_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
+}
+
+static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
+{
+ struct pipe_screen *screen = rctx->b.b.screen;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
+ struct r600_resource *rbuffer;
+
+ r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
+
+ if (state->enable) {
+ rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
+ r600_write_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
+ (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW));
+ r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
+ state->esgs_ring.buffer_size >> 8);
+
+ rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
+ r600_write_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
+ (r600_resource_va(screen, &rbuffer->b.b)) >> 8);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rbuffer,
+ RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SHADER_RESOURCE_RW));
+ r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
+ state->gsvs_ring.buffer_size >> 8);
+ } else {
+ r600_write_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
+ r600_write_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
+ }
+
+ r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
}
void cayman_init_common_regs(struct r600_command_buffer *cb,
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
- r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
+ r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
+ r600_store_value(cb, 0);
+ r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
}
static void cayman_init_atom_start_cs(struct r600_context *rctx)
{
struct r600_command_buffer *cb = &rctx->start_cs_cmd;
+ int tmp;
r600_init_command_buffer(cb, 256);
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
- cayman_init_common_regs(cb, rctx->chip_class,
- rctx->family, rctx->screen->info.drm_minor);
+ cayman_init_common_regs(cb, rctx->b.chip_class,
+ rctx->b.family, rctx->screen->b.info.drm_minor);
r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
- r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
- r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
- r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
+ r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
- r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
- r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
- r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
+ r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
+ for (tmp = 0; tmp < 16; tmp++) {
+ r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
+ r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
+ }
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
- r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
r600_store_value(cb, 0);
r600_store_value(cb, 0);
- if (rctx->screen->has_streamout) {
+ if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
+ eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
}
void evergreen_init_common_regs(struct r600_command_buffer *cb,
r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
}
- r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
- S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
-
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
/* The cs checker requires this register to be set. */
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
- r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
+ r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
+ r600_store_value(cb, 0);
+ r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
return;
}
enum radeon_family family;
unsigned tmp;
- if (rctx->chip_class == CAYMAN) {
+ if (rctx->b.chip_class == CAYMAN) {
cayman_init_atom_start_cs(rctx);
return;
}
r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
- evergreen_init_common_regs(cb, rctx->chip_class,
- rctx->family, rctx->screen->info.drm_minor);
+ evergreen_init_common_regs(cb, rctx->b.chip_class,
+ rctx->b.family, rctx->screen->b.info.drm_minor);
- family = rctx->family;
+ family = rctx->b.family;
switch (family) {
case CHIP_CEDAR:
default:
tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
+ r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
+ S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
+
r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
- r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
- r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
- r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
+ r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * 16);
+ for (tmp = 0; tmp < 16; tmp++) {
+ r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
+ r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
+ }
r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
- r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
r600_store_value(cb, 0);
r600_store_value(cb, 0);
- r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
- r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
- r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
+ r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0);
- if (rctx->screen->has_streamout) {
+ if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
+ eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF);
}
void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
shader->flatshade = rctx->rasterizer->flatshade;
}
+void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_command_buffer *cb = &shader->command_buffer;
+ struct r600_shader *rshader = &shader->shader;
+
+ r600_init_command_buffer(cb, 32);
+
+ r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
+ S_028890_NUM_GPRS(rshader->bc.ngpr) |
+ S_028890_STACK_SIZE(rshader->bc.nstack));
+ r600_store_context_reg(cb, R_02888C_SQ_PGM_START_ES,
+ r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
+ /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
+}
+
+void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_command_buffer *cb = &shader->command_buffer;
+ struct r600_shader *rshader = &shader->shader;
+ struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
+ unsigned gsvs_itemsize =
+ (cp_shader->ring_item_size * rshader->gs_max_out_vertices) >> 2;
+
+ r600_init_command_buffer(cb, 64);
+
+ /* VGT_GS_MODE is written by evergreen_emit_shader_stages */
+
+ r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
+
+ r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
+ S_028B38_MAX_VERT_OUT(rshader->gs_max_out_vertices));
+ r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
+ r600_conv_prim_to_gs_out(rshader->gs_output_prim));
+
+ if (rctx->screen->b.info.drm_minor >= 35) {
+ r600_store_context_reg(cb, R_028B90_VGT_GS_INSTANCE_CNT,
+ S_028B90_CNT(0) |
+ S_028B90_ENABLE(0));
+ }
+ r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
+ r600_store_value(cb, cp_shader->ring_item_size >> 2);
+ r600_store_value(cb, 0);
+ r600_store_value(cb, 0);
+ r600_store_value(cb, 0);
+
+ r600_store_context_reg(cb, R_028900_SQ_ESGS_RING_ITEMSIZE,
+ (rshader->ring_item_size) >> 2);
+
+ r600_store_context_reg(cb, R_028904_SQ_GSVS_RING_ITEMSIZE,
+ gsvs_itemsize);
+
+ r600_store_context_reg_seq(cb, R_02892C_SQ_GSVS_RING_OFFSET_1, 3);
+ r600_store_value(cb, gsvs_itemsize);
+ r600_store_value(cb, gsvs_itemsize);
+ r600_store_value(cb, gsvs_itemsize);
+
+ /* FIXME calculate these values somehow ??? */
+ r600_store_context_reg_seq(cb, R_028A54_GS_PER_ES, 3);
+ r600_store_value(cb, 0x80); /* GS_PER_ES */
+ r600_store_value(cb, 0x100); /* ES_PER_GS */
+ r600_store_value(cb, 0x2); /* GS_PER_VS */
+
+ r600_store_context_reg(cb, R_028878_SQ_PGM_RESOURCES_GS,
+ S_028878_NUM_GPRS(rshader->bc.ngpr) |
+ S_028878_STACK_SIZE(rshader->bc.nstack));
+ r600_store_context_reg(cb, R_028874_SQ_PGM_START_GS,
+ r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
+ /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
+}
+
+
void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
{
struct r600_command_buffer *cb = &shader->command_buffer;
r600_store_context_reg(cb, R_028860_SQ_PGM_RESOURCES_VS,
S_028860_NUM_GPRS(rshader->bc.ngpr) |
S_028860_STACK_SIZE(rshader->bc.nstack));
+ if (rshader->vs_position_window_space) {
+ r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
+ S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
+ } else {
+ r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
+ S_028818_VTX_W0_FMT(1) |
+ S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
+ S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
+ S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
+
+ }
r600_store_context_reg(cb, R_02885C_SQ_PGM_START_VS,
r600_resource_va(ctx->screen, (void *)shader->bo) >> 8);
/* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
- S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
+ S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
+ S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
+ S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
+ S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer);
}
void *evergreen_create_resolve_blend(struct r600_context *rctx)
memset(&blend, 0, sizeof(blend));
blend.independent_blend_enable = true;
blend.rt[0].colormask = 0xf;
- return evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
+ return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
}
void *evergreen_create_decompress_blend(struct r600_context *rctx)
memset(&blend, 0, sizeof(blend));
blend.independent_blend_enable = true;
blend.rt[0].colormask = 0xf;
- return evergreen_create_blend_state_mode(&rctx->context, &blend, mode);
+ return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
+}
+
+void *evergreen_create_fastclear_blend(struct r600_context *rctx)
+{
+ struct pipe_blend_state blend;
+ unsigned mode = V_028808_CB_ELIMINATE_FAST_CLEAR;
+
+ memset(&blend, 0, sizeof(blend));
+ blend.independent_blend_enable = true;
+ blend.rt[0].colormask = 0xf;
+ return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
}
void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
{
struct pipe_depth_stencil_alpha_state dsa = {{0}};
- return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+ return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
}
void evergreen_update_db_shader_control(struct r600_context * rctx)
{
- bool dual_export = rctx->framebuffer.export_16bpc &&
- !rctx->ps_shader->current->ps_depth_export;
+ bool dual_export;
+ unsigned db_shader_control;
+
+ if (!rctx->ps_shader) {
+ return;
+ }
- unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
- S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
- S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
- V_02880C_EXPORT_DB_FULL) |
- S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
+ dual_export = rctx->framebuffer.export_16bpc &&
+ !rctx->ps_shader->current->ps_depth_export;
+
+ db_shader_control = rctx->ps_shader->current->db_shader_control |
+ S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
+ S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO :
+ V_02880C_EXPORT_DB_FULL) |
+ S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
/* When alpha test is enabled we can't trust the hw to make the proper
* decision on the order in which ztest should be run related to fragment
unsigned pitch,
unsigned bpp)
{
- struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
uint64_t base, addr;
- /* make sure that the dma ring is only one active */
- rctx->rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
-
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
/* downcast linear aligned to linear to simplify test */
non_disp_tiling = 1;
y = 0;
- sub_cmd = 0x8;
+ sub_cmd = EG_DMA_COPY_TILED;
lbpp = util_logbase2(bpp);
- pitch_tile_max = ((pitch / bpp) >> 3) - 1;
- nbanks = eg_num_banks(rctx->screen->tiling_info.num_banks);
+ pitch_tile_max = ((pitch / bpp) / 8) - 1;
+ nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
if (dst_mode == RADEON_SURF_MODE_LINEAR) {
/* T2L */
array_mode = evergreen_array_mode(src_mode);
- slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) >> 6;
+ slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
bank_w = eg_bank_wh(rsrc->surface.bankw);
mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
tile_split = eg_tile_split(rsrc->surface.tile_split);
- base += r600_resource_va(&rctx->screen->screen, src);
- addr += r600_resource_va(&rctx->screen->screen, dst);
+ base += r600_resource_va(&rctx->screen->b.b, src);
+ addr += r600_resource_va(&rctx->screen->b.b, dst);
} else {
/* L2T */
array_mode = evergreen_array_mode(dst_mode);
- slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) >> 6;
+ slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
bank_w = eg_bank_wh(rdst->surface.bankw);
mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
tile_split = eg_tile_split(rdst->surface.tile_split);
- base += r600_resource_va(&rctx->screen->screen, dst);
- addr += r600_resource_va(&rctx->screen->screen, src);
+ base += r600_resource_va(&rctx->screen->b.b, dst);
+ addr += r600_resource_va(&rctx->screen->b.b, src);
}
- size = (copy_height * pitch) >> 2;
- ncopy = (size / 0x000fffff) + !!(size % 0x000fffff);
- r600_need_dma_space(rctx, ncopy * 9);
+ size = (copy_height * pitch) / 4;
+ ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE);
+ r600_need_dma_space(&rctx->b, ncopy * 9);
for (i = 0; i < ncopy; i++) {
cheight = copy_height;
- if (((cheight * pitch) >> 2) > 0x000fffff) {
- cheight = (0x000fffff << 2) / pitch;
+ if (((cheight * pitch) / 4) > EG_DMA_COPY_MAX_SIZE) {
+ cheight = (EG_DMA_COPY_MAX_SIZE * 4) / pitch;
}
- size = (cheight * pitch) >> 2;
+ size = (cheight * pitch) / 4;
/* emit reloc before writting cs so that cs is always in consistent state */
- r600_context_bo_reloc(rctx, &rctx->rings.dma, &rsrc->resource, RADEON_USAGE_READ);
- r600_context_bo_reloc(rctx, &rctx->rings.dma, &rdst->resource, RADEON_USAGE_WRITE);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rsrc->resource,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
+ r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, &rdst->resource,
+ RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size);
cs->buf[cs->cdw++] = base >> 8;
cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) |
}
}
-boolean evergreen_dma_blit(struct pipe_context *ctx,
- struct pipe_resource *dst,
- unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src,
- unsigned src_level,
- const struct pipe_box *src_box)
+static void evergreen_dma_copy(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
unsigned src_w, dst_w;
+ unsigned src_x, src_y;
+ unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
- if (rctx->rings.dma.cs == NULL) {
- return FALSE;
+ if (rctx->b.rings.dma.cs == NULL) {
+ goto fallback;
}
- if (src->format != dst->format) {
- return FALSE;
+
+ if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
+ evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
+ return;
}
+ if (src->format != dst->format || src_box->depth > 1 ||
+ rdst->dirty_level_mask != 0) {
+ goto fallback;
+ }
+
+ if (rsrc->dirty_level_mask) {
+ ctx->flush_resource(ctx, src);
+ }
+
+ src_x = util_format_get_nblocksx(src->format, src_box->x);
+ dst_x = util_format_get_nblocksx(src->format, dst_x);
+ src_y = util_format_get_nblocksy(src->format, src_box->y);
+ dst_y = util_format_get_nblocksy(src->format, dst_y);
+
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* FIXME evergreen can do partial blit */
- return FALSE;
+ goto fallback;
}
/* the x test here are currently useless (because we don't support partial blit)
* but keep them around so we don't forget about those
*/
- if ((src_pitch & 0x7) || (src_box->x & 0x7) || (dst_x & 0x7) || (src_box->y & 0x7) || (dst_y & 0x7)) {
- return FALSE;
+ if (src_pitch % 8 || src_box->x % 8 || dst_x % 8 || src_box->y % 8 || dst_y % 8) {
+ goto fallback;
}
/* 128 bpp surfaces require non_disp_tiling for both
* DMA only supports it on the tiled side. As such
* the tile order is backwards after a L2T/T2L packet.
*/
- if ((rctx->chip_class == CAYMAN) &&
+ if ((rctx->b.chip_class == CAYMAN) &&
(src_mode != dst_mode) &&
(util_format_get_blocksize(src->format) >= 16)) {
- return FALSE;
+ goto fallback;
}
if (src_mode == dst_mode) {
*/
src_offset= rsrc->surface.level[src_level].offset;
src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
- src_offset += src_box->y * src_pitch + src_box->x * bpp;
+ src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.level[dst_level].offset;
dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
- evergreen_dma_copy(rctx, dst, src, dst_offset, src_offset,
+ evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
src_box->height * src_pitch);
} else {
evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
- src, src_level, src_box->x, src_box->y, src_box->z,
+ src, src_level, src_x, src_y, src_box->z,
copy_height, dst_pitch, bpp);
}
- return TRUE;
+ return;
+
+fallback:
+ ctx->resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
+ src, src_level, src_box);
}
void evergreen_init_state_functions(struct r600_context *rctx)
{
unsigned id = 4;
-
+ int i;
/* !!!
* To avoid GPU lockup registers must be emited in a specific order
* (no kidding ...). The order below is important and have been
r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 7);
- if (rctx->chip_class == EVERGREEN) {
+ if (rctx->b.chip_class == EVERGREEN) {
r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
} else {
r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6);
r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
- r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4);
+ for (i = 0; i < 16; i++) {
+ r600_init_atom(rctx, &rctx->viewport[i].atom, id++, r600_emit_viewport_state, 8);
+ r600_init_atom(rctx, &rctx->scissor[i].atom, id++, evergreen_emit_scissor_state, 4);
+ rctx->viewport[i].idx = i;
+ rctx->scissor[i].idx = i;
+ }
r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
- r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
- r600_init_atom(rctx, &rctx->streamout.begin_atom, id++, r600_emit_streamout_begin, 0);
+ rctx->atoms[id++] = &rctx->b.streamout.begin_atom;
+ rctx->atoms[id++] = &rctx->b.streamout.enable_atom;
r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23);
r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0);
-
- rctx->context.create_blend_state = evergreen_create_blend_state;
- rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
- rctx->context.create_rasterizer_state = evergreen_create_rs_state;
- rctx->context.create_sampler_state = evergreen_create_sampler_state;
- rctx->context.create_sampler_view = evergreen_create_sampler_view;
- rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
- rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
- rctx->context.set_scissor_states = evergreen_set_scissor_states;
-
- if (rctx->chip_class == EVERGREEN)
- rctx->context.get_sample_position = evergreen_get_sample_position;
+ r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0);
+ r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0);
+ r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 6);
+ r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
+
+ rctx->b.b.create_blend_state = evergreen_create_blend_state;
+ rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
+ rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
+ rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
+ rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
+ rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
+ rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
+ rctx->b.b.set_scissor_states = evergreen_set_scissor_states;
+
+ if (rctx->b.chip_class == EVERGREEN)
+ rctx->b.b.get_sample_position = evergreen_get_sample_position;
else
- rctx->context.get_sample_position = cayman_get_sample_position;
+ rctx->b.b.get_sample_position = cayman_get_sample_position;
+ rctx->b.dma_copy = evergreen_dma_copy;
+
evergreen_init_compute_state_functions(rctx);
}
projects / mesa.git / blobdiff