r600g: Make sure to initialize DB_DEPTH_CONTROL register for compute

[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index c0615767be272995d95f2016bab13caaf9b0de9c..f244e8a5cadc275ece78ab25b2053c7c9552b21c 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -643,13 +643,6 @@ boolean evergreen_is_format_supported(struct pipe_screen *screen,
                default:
                        return FALSE;
                }
-
-               /* require render-target support for multisample resources */
-               if (util_format_is_depth_or_stencil(format)) {
-                       usage |= PIPE_BIND_DEPTH_STENCIL;
-               } else {
-                       usage |= PIPE_BIND_RENDER_TARGET;
-               }
        }
 
        if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
@@ -921,7 +914,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
        } else {
                r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
                                        S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
-                                       S_028C08_QUANT_MODE(V_028C08_X_1_4096TH));
+                                       S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
        }
        r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
        r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
@@ -1122,43 +1115,13 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
        return &view->base;
 }
 
-static void evergreen_set_clip_state(struct pipe_context *ctx,
-                               const struct pipe_clip_state *state)
+static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
 {
-       struct r600_context *rctx = (struct r600_context *)ctx;
-       struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-       struct pipe_constant_buffer cb;
-
-       if (rstate == NULL)
-               return;
-
-       rctx->clip = *state;
-       rstate->id = R600_PIPE_STATE_CLIP;
-       for (int i = 0; i < 6; i++) {
-               r600_pipe_state_add_reg(rstate,
-                                       R_0285BC_PA_CL_UCP0_X + i * 16,
-                                       fui(state->ucp[i][0]));
-               r600_pipe_state_add_reg(rstate,
-                                       R_0285C0_PA_CL_UCP0_Y + i * 16,
-                                       fui(state->ucp[i][1]) );
-               r600_pipe_state_add_reg(rstate,
-                                       R_0285C4_PA_CL_UCP0_Z + i * 16,
-                                       fui(state->ucp[i][2]));
-               r600_pipe_state_add_reg(rstate,
-                                       R_0285C8_PA_CL_UCP0_W + i * 16,
-                                       fui(state->ucp[i][3]));
-       }
-
-       free(rctx->states[R600_PIPE_STATE_CLIP]);
-       rctx->states[R600_PIPE_STATE_CLIP] = rstate;
-       r600_context_pipe_state_set(rctx, rstate);
+       struct radeon_winsys_cs *cs = rctx->cs;
+       struct pipe_clip_state *state = &rctx->clip_state.state;
 
-       cb.buffer = NULL;
-       cb.user_buffer = state->ucp;
-       cb.buffer_offset = 0;
-       cb.buffer_size = 4*4*8;
-       ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
-       pipe_resource_reference(&cb.buffer, NULL);
+       r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP0_X, 6*4);
+       r600_write_array(cs, 6*4, (unsigned*)state);
 }
 
 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
@@ -2180,29 +2143,30 @@ void evergreen_init_state_functions(struct r600_context *rctx)
        r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
        r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
 
+       r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 6);
+       r600_init_atom(rctx, &rctx->vgt2_state.atom, id++, r600_emit_vgt2_state, 3);
+
        if (rctx->chip_class == EVERGREEN) {
                r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
        } else {
                r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
        }
        rctx->sample_mask.sample_mask = ~0;
-       r600_atom_dirty(rctx, &rctx->sample_mask.atom);
-
-       r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 0);
-       r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 
        r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
-       r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
-
+       r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
+       r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
+       r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
+       r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
        r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
-       r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
+       r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
+       r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
 
        rctx->context.create_blend_state = evergreen_create_blend_state;
        rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
        rctx->context.create_rasterizer_state = evergreen_create_rs_state;
        rctx->context.create_sampler_state = evergreen_create_sampler_state;
        rctx->context.create_sampler_view = evergreen_create_sampler_view;
-       rctx->context.set_clip_state = evergreen_set_clip_state;
        rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
        rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
        rctx->context.set_scissor_state = evergreen_set_scissor_state;
@@ -2559,6 +2523,9 @@ void evergreen_init_common_regs(struct r600_command_buffer *cb,
        r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
        r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
 
+       /* The cs checker requires this register to be set. */
+       r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
+
        r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
        r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
 
@@ -2899,7 +2866,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx)
 
        r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
 
-       r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
        if (rctx->screen->has_streamout) {
                r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
        }