#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7
#define PKT3_NOP 0x10
+#define PKT3_DISPATCH_DIRECT 0x15
+#define PKT3_DISPATCH_INDIRECT 0x16
#define PKT3_INDIRECT_BUFFER_END 0x17
#define PKT3_SET_PREDICATION 0x20
#define PKT3_REG_RMW 0x21
#define G_008CF0_ALU_UPDATE_FIFO_HIWATER(x) (((x) >> 24) & 0x1F)
#define C_008CF0_ALU_UPDATE_FIFO_HIWATER(x) 0xE0FFFFFF
+#define R_008E20_SQ_STATIC_THREAD_MGMT1 0x8E20
+#define R_008E24_SQ_STATIC_THREAD_MGMT2 0x8E24
+#define R_008E28_SQ_STATIC_THREAD_MGMT3 0x8E28
+
+#define R_00899C_VGT_COMPUTE_START_X 0x0000899C
+#define R_0089A0_VGT_COMPUTE_START_Y 0x000089A0
+#define R_0089A4_VGT_COMPUTE_START_Z 0x000089A4
+#define R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE 0x000089AC
+
#define R_009100_SPI_CONFIG_CNTL 0x00009100
#define R_00913C_SPI_CONFIG_CNTL_1 0x0000913C
#define S_00913C_VTX_DONE_DELAY(x) (((x) & 0xF) << 0)
#define G_028410_ALPHA_TEST_BYPASS(x) (((x) >> 8) & 0x1)
#define C_028410_ALPHA_TEST_BYPASS 0xFFFFFEFF
+#define R_0286EC_SPI_COMPUTE_NUM_THREAD_X 0x0286EC
+#define R_0286F0_SPI_COMPUTE_NUM_THREAD_Y 0x0286F0
+#define R_0286F4_SPI_COMPUTE_NUM_THREAD_Z 0x0286F4
+#define R_028B74_VGT_DISPATCH_INITIATOR 0x028B74
+
#define R_028800_DB_DEPTH_CONTROL 0x028800
#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
#define S_028808_MODE(x) (((x) & 0x7) << 4)
#define G_028808_MODE(x) (((x) >> 4) & 0x7)
#define C_028808_MODE 0xFFFFFF8F
+#define V_028808_CB_DISABLE 0x00000000
+#define V_028808_CB_NORMAL 0x00000001
+#define V_028808_CB_ELIMINATE_FAST_CLEAR 0x00000002
+#define V_028808_CB_RESOLVE 0x00000003
+#define V_028808_CB_DECOMPRESS 0x00000004
+#define V_028808_CB_FASK_DECOMPRESS 0x00000005
#define S_028808_ROP3(x) (((x) & 0xFF) << 16)
#define G_028808_ROP3(x) (((x) >> 16) & 0xFF)
#define C_028808_ROP3 0xFF00FFFF
#define S_02880C_DUAL_EXPORT_ENABLE(x) (((x) & 0x1) << 9)
#define G_02880C_DUAL_EXPORT_ENABLE(x) (((x) >> 9) & 0x1)
#define C_02880C_DUAL_EXPORT_ENABLE 0xFFFFFDFF
+#define S_02880C_DB_SOURCE_FORMAT(x) (((x) & 0x3) << 13)
+#define G_02880C_DB_SOURCE_FORMAT(x) (((x) >> 13) & 0x3)
+#define C_02880C_DB_SOURCE_FORMAT 0xFFFF9FFF
+#define V_02880C_EXPORT_DB_FULL 0x00
+#define V_02880C_EXPORT_DB_FOUR16 0x01
+#define V_02880C_EXPORT_DB_TWO 0x02
+#define S_02880C_ALPHA_TO_MASK_DISABLE(x) (((x) & 0x1) << 12)
+
#define R_028A00_PA_SU_POINT_SIZE 0x028A00
#define S_028A00_HEIGHT(x) (((x) & 0xFFFF) << 0)
#define G_028A00_HEIGHT(x) (((x) >> 0) & 0xFFFF)
#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3)
#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3)
#define C_028A40_CUT_MODE 0xFFFFFFE7
+#define S_028A40_COMPUTE_MODE(x) (x << 14)
+#define S_028A40_PARTIAL_THD_AT_EOI(x) (x << 17)
#define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C
#define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0)
#define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
#define G_028848_ALLOW_DOUBLE_DENORM_OUT(x) (((x) >> 7) & 0x1)
#define C_028848_ALLOW_DOUBLE_DENORM_OUT 0xFFFFFF7F
+#define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
+#define S_0288D4_NUM_GPRS(x) (((x) & 0xFF) << 0)
+#define G_0288D4_NUM_GPRS(x) (((x) >> 0) & 0xFF)
+#define C_0288D4_NUM_GPRS 0xFFFFFF00
+#define S_0288D4_STACK_SIZE(x) (((x) & 0xFF) << 8)
+#define G_0288D4_STACK_SIZE(x) (((x) >> 8) & 0xFF)
+#define C_0288D4_STACK_SIZE 0xFFFF00FF
+#define S_0288D4_DX10_CLAMP(x) (((x) & 0x1) << 21)
+#define G_0288D4_DX10_CLAMP(x) (((x) >> 21) & 0x1)
+#define C_0288D4_DX10_CLAMP 0xFFDFFFFF
+#define S_0288D4_PRIME_CACHE_ON_DRAW(x) (((x) & 0x1) << 23)
+#define G_0288D4_PRIME_CACHE_ON_DRAW(x) (((x) >> 23) & 0x1)
+#define S_0288D4_UNCACHED_FIRST_INST(x) (((x) & 0x1) << 28)
+#define G_0288D4_UNCACHED_FIRST_INST(x) (((x) >> 28) & 0x1)
+#define C_0288D4_UNCACHED_FIRST_INST 0xEFFFFFFF
+#define S_0288D4_CLAMP_CONSTS(x) (((x) & 0x1) << 31)
+#define G_0288D4_CLAMP_CONSTS(x) (((x) >> 31) & 0x1)
+#define C_0288D4_CLAMP_CONSTS 0x7FFFFFFF
+
+#define R_0288D8_SQ_PGM_RESOURCES_LS_2 0x0288d8
+
+
+#define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
+#define S_0288D4_NUM_GPRS(x) (((x) & 0xFF) << 0)
+#define G_0288D4_NUM_GPRS(x) (((x) >> 0) & 0xFF)
+#define C_0288D4_NUM_GPRS 0xFFFFFF00
+#define S_0288D4_STACK_SIZE(x) (((x) & 0xFF) << 8)
+#define G_0288D4_STACK_SIZE(x) (((x) >> 8) & 0xFF)
+#define C_0288D4_STACK_SIZE 0xFFFF00FF
+#define S_0288D4_DX10_CLAMP(x) (((x) & 0x1) << 21)
+#define G_0288D4_DX10_CLAMP(x) (((x) >> 21) & 0x1)
+#define C_0288D4_DX10_CLAMP 0xFFDFFFFF
+#define S_0288D4_PRIME_CACHE_ON_DRAW(x) (((x) & 0x1) << 23)
+#define G_0288D4_PRIME_CACHE_ON_DRAW(x) (((x) >> 23) & 0x1)
+#define S_0288D4_UNCACHED_FIRST_INST(x) (((x) & 0x1) << 28)
+#define G_0288D4_UNCACHED_FIRST_INST(x) (((x) >> 28) & 0x1)
+#define C_0288D4_UNCACHED_FIRST_INST 0xEFFFFFFF
+#define S_0288D4_CLAMP_CONSTS(x) (((x) & 0x1) << 31)
+#define G_0288D4_CLAMP_CONSTS(x) (((x) >> 31) & 0x1)
+#define C_0288D4_CLAMP_CONSTS 0x7FFFFFFF
+
+#define R_0288D8_SQ_PGM_RESOURCES_LS_2 0x0288d8
+
+
#define R_028644_SPI_PS_INPUT_CNTL_0 0x028644
#define S_028644_SEMANTIC(x) (((x) & 0xFF) << 0)
#define G_028644_SEMANTIC(x) (((x) >> 0) & 0xFF)
#define R_0286DC_SPI_FOG_CNTL 0x000286DC
#define R_0286E4_SPI_PS_IN_CONTROL_2 0x000286E4
#define R_0286E8_SPI_COMPUTE_INPUT_CNTL 0x000286E8
+#define S_0286E8_TID_IN_GROUP_ENA 1
+#define S_0286E8_TGID_ENA 2
+#define S_0286E8_DISABLE_INDEX_PACK 4
+#define R_028720_GDS_ADDR_BASE 0x00028720
+#define R_028724_GDS_ADDR_SIZE 0x00028724
+#define R_028728_GDS_ORDERED_WAVE_PER_SE 0x00028728
#define R_028784_CB_BLEND1_CONTROL 0x00028784
#define R_028788_CB_BLEND2_CONTROL 0x00028788
#define R_02878C_CB_BLEND3_CONTROL 0x0002878C
#define C_02884C_EXPORT_Z 0xFFFFFFFE
#define R_02885C_SQ_PGM_START_VS 0x0002885C
#define R_0288A4_SQ_PGM_START_FS 0x000288A4
+#define R_0288D0_SQ_PGM_START_LS 0x000288d0
#define R_0288A8_SQ_PGM_RESOURCES_FS 0x000288A8
#define R_0288EC_SQ_LDS_ALLOC_PS 0x000288EC
#define R_028900_SQ_ESGS_RING_ITEMSIZE 0x00028900
#define R_028B50_VGT_STRMOUT_BASE_OFFSET_HI_3 0x028B50
#define R_028B54_VGT_SHADER_STAGES_EN 0x00028B54
#define R_028B70_DB_ALPHA_TO_MASK 0x00028B70
+#define S_028B70_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
+#define S_028B70_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x3) << 8)
+#define S_028B70_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x3) << 10)
+#define S_028B70_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x3) << 12)
+#define S_028B70_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x3) << 14)
+#define S_028B70_OFFSET_ROUND(x) (((x) & 0x1) << 16)
#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x00028B78
#define S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) & 0xFF) << 0)
#define G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x) (((x) >> 0) & 0xFF)
#define S_028B98_STREAM_2_BUFFER_EN(x) (((x) & 0xf) << 8)
#define S_028B98_STREAM_3_BUFFER_EN(x) (((x) & 0xf) << 12)
#define R_028C00_PA_SC_LINE_CNTL 0x00028C00
+#define S_028C00_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9)
+#define G_028C00_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
+#define C_028C00_EXPAND_LINE_WIDTH 0xFFFFFDFF
+#define S_028C00_LAST_PIXEL(x) (((x) & 0x1) << 10)
+#define G_028C00_LAST_PIXEL(x) (((x) >> 10) & 0x1)
+#define C_028C00_LAST_PIXEL 0xFFFFFBFF
#define R_028C04_PA_SC_AA_CONFIG 0x00028C04
+#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)
+#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)
+#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xf) << 13)
#define R_028C08_PA_SU_VTX_CNTL 0x00028C08
#define S_028C08_PIX_CENTER_HALF(x) (((x) & 0x1) << 0)
#define G_028C08_PIX_CENTER_HALF(x) (((x) >> 0) & 0x1)
#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x00028C14
#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ 0x00028C18
#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 0x00028C1C
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_1 0x00028C20
+#define R_028C24_PA_SC_AA_SAMPLE_LOCS_2 0x00028C24
+#define R_028C28_PA_SC_AA_SAMPLE_LOCS_3 0x00028C28
+#define R_028C2C_PA_SC_AA_SAMPLE_LOCS_4 0x00028C2C
+#define R_028C30_PA_SC_AA_SAMPLE_LOCS_5 0x00028C30
+#define R_028C34_PA_SC_AA_SAMPLE_LOCS_6 0x00028C34
+#define R_028C38_PA_SC_AA_SAMPLE_LOCS_7 0x00028C38
#define R_028C3C_PA_SC_AA_MASK 0x00028C3C
#define R_028C60_CB_COLOR0_BASE 0x00028C60
#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
#define ENDIAN_8IN32 2
#define ENDIAN_8IN64 3
+#define CM_R_0286FC_SPI_LDS_MGMT 0x286fc
+#define S_0286FC_NUM_PS_LDS(x) ((x) & 0xff)
+#define S_0286FC_NUM_LS_LDS(x) ((x) & 0xff) << 8
#define CM_R_0288E8_SQ_LDS_ALLOC 0x000288E8
#define CM_R_028804_DB_EQAA 0x00028804
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