r600g: implement timestamp query and get_timestamp hook

[mesa.git] / src / gallium / drivers / r600 / evergreend.h

diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 5d57ce3a9a2bf552422b8af7fbc3e3c7ad61326b..d1b3cd33bb752a6284a3ee58c0fcbb3d62ad3057 100644 (file)
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -116,11 +116,6 @@
 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
 
-#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
-
-/*Evergreen Compute packet3*/
-#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
-
 /* Registers */
 #define R_0084FC_CP_STRMOUT_CNTL                    0x000084FC
 #define   S_0084FC_OFFSET_UPDATE_DONE(x)               (((x) & 0x1) << 0)
@@ -482,6 +477,12 @@
 #define   S_028808_MODE(x)                             (((x) & 0x7) << 4)
 #define   G_028808_MODE(x)                             (((x) >> 4) & 0x7)
 #define   C_028808_MODE                                0xFFFFFF8F
+#define      V_028808_CB_DISABLE                       0x00000000
+#define      V_028808_CB_NORMAL                        0x00000001
+#define      V_028808_CB_ELIMINATE_FAST_CLEAR          0x00000002
+#define      V_028808_CB_RESOLVE                       0x00000003
+#define      V_028808_CB_DECOMPRESS                    0x00000004
+#define      V_028808_CB_FASK_DECOMPRESS               0x00000005
 #define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
 #define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
 #define   C_028808_ROP3                                0xFF00FFFF
@@ -746,6 +747,14 @@
 #define   S_02880C_DUAL_EXPORT_ENABLE(x)               (((x) & 0x1) << 9)
 #define   G_02880C_DUAL_EXPORT_ENABLE(x)               (((x) >> 9) & 0x1)
 #define   C_02880C_DUAL_EXPORT_ENABLE                  0xFFFFFDFF
+#define   S_02880C_DB_SOURCE_FORMAT(x)                 (((x) & 0x3) << 13)
+#define   G_02880C_DB_SOURCE_FORMAT(x)                 (((x) >> 13) & 0x3)
+#define   C_02880C_DB_SOURCE_FORMAT                    0xFFFF9FFF
+#define     V_02880C_EXPORT_DB_FULL                    0x00
+#define     V_02880C_EXPORT_DB_FOUR16                  0x01
+#define     V_02880C_EXPORT_DB_TWO                     0x02
+#define   S_02880C_ALPHA_TO_MASK_DISABLE(x)            (((x) & 0x1) << 12)
+
 #define R_028A00_PA_SU_POINT_SIZE                    0x028A00
 #define   S_028A00_HEIGHT(x)                           (((x) & 0xFFFF) << 0)
 #define   G_028A00_HEIGHT(x)                           (((x) >> 0) & 0xFFFF)
@@ -1892,6 +1901,12 @@
 #define R_028B50_VGT_STRMOUT_BASE_OFFSET_HI_3       0x028B50
 #define R_028B54_VGT_SHADER_STAGES_EN                0x00028B54
 #define R_028B70_DB_ALPHA_TO_MASK                    0x00028B70
+#define   S_028B70_ALPHA_TO_MASK_ENABLE(x)             (((x) & 0x1) << 0)
+#define   S_028B70_ALPHA_TO_MASK_OFFSET0(x)            (((x) & 0x3) << 8)
+#define   S_028B70_ALPHA_TO_MASK_OFFSET1(x)            (((x) & 0x3) << 10)
+#define   S_028B70_ALPHA_TO_MASK_OFFSET2(x)            (((x) & 0x3) << 12)
+#define   S_028B70_ALPHA_TO_MASK_OFFSET3(x)            (((x) & 0x3) << 14)
+#define   S_028B70_OFFSET_ROUND(x)                     (((x) & 0x1) << 16)
 #define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x00028B78
 #define   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
 #define   G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
@@ -1928,7 +1943,16 @@
 #define   S_028B98_STREAM_2_BUFFER_EN(x)               (((x) & 0xf) << 8)
 #define   S_028B98_STREAM_3_BUFFER_EN(x)               (((x) & 0xf) << 12)
 #define R_028C00_PA_SC_LINE_CNTL                     0x00028C00
+#define   S_028C00_EXPAND_LINE_WIDTH(x)                (((x) & 0x1) << 9)
+#define   G_028C00_EXPAND_LINE_WIDTH(x)                (((x) >> 9) & 0x1)
+#define   C_028C00_EXPAND_LINE_WIDTH                   0xFFFFFDFF
+#define   S_028C00_LAST_PIXEL(x)                       (((x) & 0x1) << 10)
+#define   G_028C00_LAST_PIXEL(x)                       (((x) >> 10) & 0x1)
+#define   C_028C00_LAST_PIXEL                          0xFFFFFBFF
 #define R_028C04_PA_SC_AA_CONFIG                     0x00028C04
+#define   S_028C04_MSAA_NUM_SAMPLES(x)                  (((x) & 0x3) << 0)
+#define   S_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) & 0x1) << 4)
+#define   S_028C04_MAX_SAMPLE_DIST(x)                  (((x) & 0xf) << 13)
 #define R_028C08_PA_SU_VTX_CNTL                      0x00028C08
 #define   S_028C08_PIX_CENTER_HALF(x)                  (((x) & 0x1) << 0)
 #define   G_028C08_PIX_CENTER_HALF(x)                  (((x) >> 0) & 0x1)
@@ -1938,6 +1962,13 @@
 #define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x00028C14
 #define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x00028C18
 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_0              0x00028C1C
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_1              0x00028C20
+#define R_028C24_PA_SC_AA_SAMPLE_LOCS_2              0x00028C24
+#define R_028C28_PA_SC_AA_SAMPLE_LOCS_3              0x00028C28
+#define R_028C2C_PA_SC_AA_SAMPLE_LOCS_4              0x00028C2C
+#define R_028C30_PA_SC_AA_SAMPLE_LOCS_5              0x00028C30
+#define R_028C34_PA_SC_AA_SAMPLE_LOCS_6              0x00028C34
+#define R_028C38_PA_SC_AA_SAMPLE_LOCS_7              0x00028C38
 #define R_028C3C_PA_SC_AA_MASK                       0x00028C3C
 #define R_028C60_CB_COLOR0_BASE                      0x00028C60
 #define R_028C6C_CB_COLOR0_VIEW                      0x00028C6C