winsys/amdgpu: pass PIPE_CONFIG to addrlib on texture import

[mesa.git] / src / gallium / drivers / r600 / evergreend.h

diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 8fed4c86468f343e63931beb8760c98f36a875dc..ece421e3d3343bbabe4035bec2600879d8cc36ae 100644 (file)
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -492,8 +492,8 @@
 #define   C_028B6C_BUFFER_ACCESS_MODE                                 0xFFFFFDFF
 #define     V_028B6C_PATCH_MAJOR                                    0x00
 #define     V_028B6C_TF_MAJOR                                       0x01
-#define   S_028B6C_NUM_DS_WAVES_PER_SIMD                              (((x) & 0xf) << 10)
-#define   G_028B6C_NUM_DS_WAVES_PER_SIMD                              (((x) >> 10) & 0xF)
+#define   S_028B6C_NUM_DS_WAVES_PER_SIMD(x)                           (((x) & 0xf) << 10)
+#define   G_028B6C_NUM_DS_WAVES_PER_SIMD(x)                           (((x) >> 10) & 0xF)
 #define   C_028B6C_NUM_DS_WAVES_PER_SIMD                              0xFFFFC3FF
 
 #define R_028B74_VGT_DISPATCH_INITIATOR              0x028B74
@@ -1202,11 +1202,11 @@
 #define   G_030014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
 #define   C_030014_LAST_ARRAY                          0xC001FFFF
 #define R_030018_SQ_TEX_RESOURCE_WORD6_0             0x030018
-/* FMASK_BANK_HEIGHT and MAX_ANISO share the first two bits.
+/* FMASK_BANK_HEIGHT and MAX_ANISO_RATIO share the first two bits.
  * The former is only used with MSAA textures. */
-#define   S_030018_MAX_ANISO(x)                        (((x) & 0x7) << 0)
-#define   G_030018_MAX_ANISO(x)                        (((x) >> 0) & 0x7)
-#define   C_030018_MAX_ANISO                           0xFFFFFFF8
+#define   S_030018_MAX_ANISO_RATIO(x)                  (((x) & 0x7) << 0)
+#define   G_030018_MAX_ANISO_RATIO(x)                  (((x) >> 0) & 0x7)
+#define   C_030018_MAX_ANISO_RATIO                     0xFFFFFFF8
 #define   S_030018_FMASK_BANK_HEIGHT(x)                (((x) & 0x3) << 0)
 #define   S_030018_PERF_MODULATION(x)                  (((x) & 0x7) << 3)
 #define   G_030018_PERF_MODULATION(x)                  (((x) >> 3) & 0x7)
@@ -1344,9 +1344,9 @@
 #define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 15)
 #define   G_03C000_MIP_FILTER(x)                       (((x) >> 15) & 0x3)
 #define   C_03C000_MIP_FILTER                          0xFFFE7FFF
-#define   S_03C000_MAX_ANISO(x)                        (((x) & 0x7) << 17)
-#define   G_03C000_MAX_ANISO(x)                        (((x) >> 17) & 0x7)
-#define   C_03C000_MAX_ANISO                           0xFFF1FFFF
+#define   S_03C000_MAX_ANISO_RATIO(x)                  (((x) & 0x7) << 17)
+#define   G_03C000_MAX_ANISO_RATIO(x)                  (((x) >> 17) & 0x7)
+#define   C_03C000_MAX_ANISO_RATIO                     0xFFF1FFFF
 #define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 20)
 #define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 20) & 0x3)
 #define   C_03C000_BORDER_COLOR_TYPE                   0xFFCFFFFF
@@ -1735,7 +1735,7 @@
 #define   S_028000_COPY_SAMPLE(x)                      (((x) & 0x7) << 8)
 #define   S_028000_COLOR_DISABLE(x)                    (((x) & 0x1) << 12)
 #define R_028004_DB_COUNT_CONTROL                    0x00028004
-#define   S_028004_ZPASS_INCREMENT_DISABLE        (((x) & 0x1) << 0)
+#define   S_028004_ZPASS_INCREMENT_DISABLE(x)     (((x) & 0x1) << 0)
 #define   S_028004_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 1)
 #define   S_028004_SAMPLE_RATE(x)                 (((x) & 0x7) << 4) /* cayman only */
 #define R_028008_DB_DEPTH_VIEW                       0x00028008
@@ -2146,20 +2146,20 @@
 #define   C_028B5C_SIZE                                               0xFFFFFF00
 #define   S_028B5C_PATCH_CP_SIZE(x)                                   (((x) & 0x1FFF) << 8)
 #define   G_028B5C_PATCH_CP_SIZE(x)                                   (((x) >> 8) & 0x1FFF)
-#define   C_028B5C_PATCH_CP_SIZE                                      0xFFFE00FF
+#define   C_028B5C_PATCH_CP_SIZE                                      0xFFE000FF
 #define R_028B60_VGT_HS_SIZE                         0x00028B60
 #define   S_028B60_SIZE(x)                                            (((x) & 0xFF) << 0)
 #define   G_028B60_SIZE(x)                                            (((x) >> 0) & 0xFF)
 #define   C_028B60_SIZE                                               0xFFFFFF00
 #define   S_028B60_PATCH_CP_SIZE(x)                                   (((x) & 0x1FFF) << 8)
 #define   G_028B60_PATCH_CP_SIZE(x)                                   (((x) >> 8) & 0x1FFF)
-#define   C_028B60_PATCH_CP_SIZE                                      0xFFFE00FF
+#define   C_028B60_PATCH_CP_SIZE                                      0xFFE000FF
 #define R_028B64_VGT_LS_HS_ALLOC                     0x00028B64
 #define   S_028B64_HS_TOTAL_OUTPUT(x)                                 (((x) & 0x1FFF) << 0)
 #define   G_028B64_HS_TOTAL_OUTPUT(x)                                 (((x) >> 0) & 0x1FFF)
 #define   C_028B64_HS_TOTAL_OUTPUT                                    0xFFFFE000
 #define   S_028B64_LS_HS_TOTAL_OUTPUT(x)                              (((x) & 0x1FFF) << 13)
-#define   C_028B64_LS_HS_TOTAL_OUTPUT(x)                              (((x) >> 13) & 0x1FFF)
+#define   G_028B64_LS_HS_TOTAL_OUTPUT(x)                              (((x) >> 13) & 0x1FFF)
 #define   C_028B64_LS_HS_TOTAL_OUTPUT                                 0xFC001FFF
 #define R_028B68_VGT_HS_PATCH_CONST                  0x00028B68
 #define   S_028B68_SIZE(x)                                            (((x) & 0x1FFF) << 0)
@@ -2501,7 +2501,6 @@
 #define CM_R_0286FC_SPI_LDS_MGMT                     0x286fc
 #define   S_0286FC_NUM_PS_LDS(x)                     ((x) & 0xff)
 #define   S_0286FC_NUM_LS_LDS(x)                     ((x) & 0xff) << 8
-#define CM_R_0288E8_SQ_LDS_ALLOC                     0x000288E8
 
 #define CM_R_028804_DB_EQAA                          0x00028804
 #define   S_028804_MAX_ANCHOR_SAMPLES(x)               (((x) & 0x7) << 0)