#include "../../winsys/radeon/drm/radeon_winsys.h"
#include "util/u_double_list.h"
-#include "util/u_vbuf.h"
+#include "util/u_transfer.h"
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
};
struct r600_resource {
- struct u_vbuf_resource b;
+ struct u_resource b;
/* Winsys objects. */
struct pb_buffer *buf;
struct r600_pipe_reg regs[R600_BLOCK_MAX_REG];
};
-struct r600_pipe_resource_state {
- unsigned id;
- uint32_t val[8];
- struct r600_resource *bo[2];
- enum radeon_bo_usage bo_usage[2];
-};
-
#define R600_BLOCK_STATUS_ENABLED (1 << 0)
#define R600_BLOCK_STATUS_DIRTY (1 << 1)
-#define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2)
struct r600_block_reloc {
struct r600_resource *bo;
#define R600_CONTEXT_DRAW_PENDING (1 << 0)
#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
+#define R600_PARTIAL_FLUSH (1 << 2)
struct r600_context;
struct r600_screen;
void r600_get_backend_mask(struct r600_context *ctx);
int r600_context_init(struct r600_context *ctx);
void r600_context_fini(struct r600_context *ctx);
+void r600_context_pipe_state_emit(struct r600_context *ctx, struct r600_pipe_state *state, unsigned pkt_flags);
void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
-void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
-void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
void r600_context_flush(struct r600_context *ctx, unsigned flags);
void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
void r600_context_streamout_begin(struct r600_context *ctx);
void r600_context_streamout_end(struct r600_context *ctx);
-void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
-void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
-void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
+void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block, unsigned pkt_flags);
int evergreen_context_init(struct r600_context *ctx);
-void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
-void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+
+void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
+ struct r600_resource *bo,
+ enum radeon_bo_usage usage);
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
uint32_t offset, uint32_t value,
- uint32_t range_id, uint32_t block_id,
- struct r600_resource *bo,
- enum radeon_bo_usage usage);
+ uint32_t range_id, uint32_t block_id);
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage);
-#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
+#define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
+#define r600_pipe_state_add_reg(state, offset, value) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset))
static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
uint32_t value)