#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
struct winsys_handle;
enum radeon_family {
#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
struct r600_pipe_reg {
- u32 value;
+ uint32_t value;
struct r600_block *block;
struct r600_resource *bo;
enum radeon_bo_usage bo_usage;
- u32 id;
+ uint32_t id;
};
struct r600_pipe_state {
struct r600_pipe_resource_state {
unsigned id;
- u32 val[8];
+ uint32_t val[8];
struct r600_resource *bo[2];
enum radeon_bo_usage bo_usage[2];
};
struct r600_block_reloc {
struct r600_resource *bo;
enum radeon_bo_usage bo_usage;
- unsigned flush_flags;
- unsigned flush_mask;
unsigned bo_pm4_index;
};
unsigned flags;
unsigned start_offset;
unsigned pm4_ndwords;
- unsigned pm4_flush_ndwords;
unsigned nbo;
- u16 nreg;
- u16 nreg_dirty;
- u32 *reg;
- u32 pm4[R600_BLOCK_MAX_REG];
+ uint16_t nreg;
+ uint16_t nreg_dirty;
+ uint32_t *reg;
+ uint32_t pm4[R600_BLOCK_MAX_REG];
unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
};
#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
#define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2)
-struct r600_context {
- struct r600_screen *screen;
- struct radeon_winsys *ws;
- struct radeon_winsys_cs *cs;
- struct pipe_context *pipe;
-
- void (*flush)(void *pipe, unsigned flags);
-
- struct r600_range *range;
- unsigned nblocks;
- struct r600_block **blocks;
- struct list_head dirty;
- struct list_head resource_dirty;
- struct list_head enable_list;
- unsigned pm4_dirty_cdwords;
- unsigned ctx_pm4_ndwords;
- unsigned init_dwords;
-
- unsigned creloc;
- struct r600_resource **bo;
-
- u32 *pm4;
- unsigned pm4_cdwords;
-
- /* The list of active queries. Only one query of each type can be active. */
- struct list_head active_query_list;
- unsigned num_cs_dw_queries_suspend;
- unsigned num_cs_dw_streamout_end;
-
- unsigned backend_mask;
- unsigned max_db; /* for OQ */
- unsigned num_dest_buffers;
- unsigned flags;
- boolean predicate_drawing;
- struct r600_range ps_resources;
- struct r600_range vs_resources;
- struct r600_range fs_resources;
- int num_ps_resources, num_vs_resources, num_fs_resources;
- boolean have_depth_texture, have_depth_fb;
-
- unsigned num_so_targets;
- struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
- boolean streamout_start;
- unsigned streamout_append_bitmask;
- unsigned *vs_so_stride_in_dw;
-};
-
struct r600_draw {
- u32 vgt_num_indices;
- u32 vgt_num_instances;
- u32 vgt_index_type;
- u32 vgt_draw_initiator;
- u32 indices_bo_offset;
+ uint32_t vgt_num_indices;
+ uint32_t vgt_num_instances;
+ uint32_t vgt_index_type;
+ uint32_t vgt_draw_initiator;
+ uint32_t indices_bo_offset;
+ unsigned db_render_override;
+ unsigned db_render_control;
struct r600_resource *indices;
};
+struct r600_context;
+struct r600_screen;
+
void r600_get_backend_mask(struct r600_context *ctx);
-int r600_context_init(struct r600_context *ctx, struct r600_screen *screen);
+int r600_context_init(struct r600_context *ctx);
void r600_context_fini(struct r600_context *ctx);
void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
int flag_wait);
void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
unsigned offset, unsigned value);
-void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
-void r600_context_flush_dest_caches(struct r600_context *ctx);
+void r600_inval_shader_cache(struct r600_context *ctx);
+void r600_inval_texture_cache(struct r600_context *ctx);
+void r600_inval_vertex_cache(struct r600_context *ctx);
+void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now);
void r600_context_streamout_begin(struct r600_context *ctx);
void r600_context_streamout_end(struct r600_context *ctx);
void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
+void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
+void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
+void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
-int evergreen_context_init(struct r600_context *ctx, struct r600_screen *screen);
+int evergreen_context_init(struct r600_context *ctx);
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
-void evergreen_context_flush_dest_caches(struct r600_context *ctx);
void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
- u32 offset, u32 value,
- u32 range_id, u32 block_id,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
struct r600_resource *bo,
enum radeon_bo_usage usage);
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- u32 offset, u32 value,
+ uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage);
-#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
+#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
- u32 value)
+ uint32_t value)
{
state->regs[state->nregs].value = value;
state->nregs++;
}
static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
- u32 value, struct r600_resource *bo,
+ uint32_t value, struct r600_resource *bo,
enum radeon_bo_usage usage)
{
state->regs[state->nregs].value = value;
projects / mesa.git / blobdiff