#include <stdint.h>
#include <stdio.h>
#include <util/u_double_list.h>
+#include <util/u_inlines.h>
#include <pipe/p_compiler.h>
#define RADEON_CTX_MAX_PM4 (64 * 1024 / 4)
enum radeon_family {
CHIP_UNKNOWN,
- CHIP_R100,
- CHIP_RV100,
- CHIP_RS100,
- CHIP_RV200,
- CHIP_RS200,
- CHIP_R200,
- CHIP_RV250,
- CHIP_RS300,
- CHIP_RV280,
- CHIP_R300,
- CHIP_R350,
- CHIP_RV350,
- CHIP_RV380,
- CHIP_R420,
- CHIP_R423,
- CHIP_RV410,
- CHIP_RS400,
- CHIP_RS480,
- CHIP_RS600,
- CHIP_RS690,
- CHIP_RS740,
- CHIP_RV515,
- CHIP_R520,
- CHIP_RV530,
- CHIP_RV560,
- CHIP_RV570,
- CHIP_R580,
CHIP_R600,
CHIP_RV610,
CHIP_RV630,
unsigned handle, unsigned *array_mode);
void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
-void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
- struct r600_bo *src);
boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo,
unsigned stride, struct winsys_handle *whandle);
static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
{
return 0;
}
+void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
+
+/* this relies on the pipe_reference being the first member of r600_bo */
+static INLINE void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst, struct r600_bo *src)
+{
+ struct r600_bo *old = *dst;
+
+ if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) {
+ r600_bo_destroy(radeon, old);
+ }
+ *dst = src;
+}
/* R600/R700 STATES */
#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
struct r600_pipe_reg {
- u32 offset;
- u32 mask;
u32 value;
- struct r600_bo *bo;
+ u32 mask;
+ struct r600_block *block;
+ struct r600_bo *bo;
+ u32 id;
};
struct r600_pipe_state {
struct r600_pipe_reg regs[R600_BLOCK_MAX_REG];
};
-static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
- u32 offset, u32 value, u32 mask,
- struct r600_bo *bo)
-{
- state->regs[state->nregs].offset = offset;
- state->regs[state->nregs].value = value;
- state->regs[state->nregs].mask = mask;
- state->regs[state->nregs].bo = bo;
- state->nregs++;
- assert(state->nregs < R600_BLOCK_MAX_REG);
-}
+struct r600_pipe_resource_state {
+ unsigned id;
+ u32 val[8];
+ struct r600_bo *bo[2];
+};
#define R600_BLOCK_STATUS_ENABLED (1 << 0)
#define R600_BLOCK_STATUS_DIRTY (1 << 1)
+#define R600_BLOCK_STATUS_RESOURCE_DIRTY (1 << 2)
+
+#define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3)
struct r600_block_reloc {
struct r600_bo *bo;
struct r600_block {
struct list_head list;
+ struct list_head enable_list;
unsigned status;
unsigned flags;
unsigned start_offset;
#define R600_QUERY_STATE_STARTED (1 << 0)
#define R600_QUERY_STATE_ENDED (1 << 1)
#define R600_QUERY_STATE_SUSPENDED (1 << 2)
+#define R600_QUERY_STATE_FLUSHED (1 << 3)
#define R600_CONTEXT_DRAW_PENDING (1 << 0)
#define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1)
unsigned nblocks;
struct r600_block **blocks;
struct list_head dirty;
+ struct list_head resource_dirty;
+ struct list_head enable_list;
unsigned pm4_ndwords;
unsigned pm4_cdwords;
unsigned pm4_dirty_cdwords;
unsigned ctx_pm4_ndwords;
+ unsigned init_dwords;
unsigned nreloc;
unsigned creloc;
struct r600_reloc *reloc;
unsigned num_dest_buffers;
unsigned flags;
boolean predicate_drawing;
+ struct r600_range ps_resources;
+ struct r600_range vs_resources;
+ struct r600_range fs_resources;
+ int num_ps_resources, num_vs_resources, num_fs_resources;
+ boolean have_depth_texture, have_depth_fb;
};
struct r600_draw {
int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
void r600_context_fini(struct r600_context *ctx);
void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
void r600_context_flush(struct r600_context *ctx);
void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
void r600_query_end(struct r600_context *ctx, struct r600_query *query);
void r600_context_queries_suspend(struct r600_context *ctx);
-void r600_context_queries_resume(struct r600_context *ctx);
+void r600_context_queries_resume(struct r600_context *ctx, boolean flushed);
void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
int flag_wait);
void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
void evergreen_context_flush_dest_caches(struct r600_context *ctx);
-void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
-void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
struct radeon *radeon_decref(struct radeon *radeon);
+void _r600_pipe_state_add_reg(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ u32 offset, u32 value, u32 mask,
+ u32 range_id, u32 block_id,
+ struct r600_bo *bo);
+
+void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
+ u32 offset, u32 value, u32 mask,
+ struct r600_bo *bo);
+#define r600_pipe_state_add_reg(state, offset, value, mask, bo) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo)
+
+static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
+ u32 value)
+{
+ state->regs[state->nregs].value = value;
+ state->nregs++;
+}
+
+static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
+ u32 value, struct r600_bo *bo)
+{
+ state->regs[state->nregs].value = value;
+ state->regs[state->nregs].bo = bo;
+ state->nregs++;
+}
+
#endif