r600g: fix RSQ of negative value on Cayman

[mesa.git] / src / gallium / drivers / r600 / r600.h

diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index d4e01d9694eebbbab081d4921714318ec3860492..7d434169d9ea9c6847214999fa12b1bb6dcc3946 100644 (file)
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -117,16 +117,8 @@ struct r600_pipe_state {
        struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 };
 
-struct r600_pipe_resource_state {
-       unsigned                        id;
-       uint32_t                        val[8];
-       struct r600_resource            *bo[2];
-       enum radeon_bo_usage            bo_usage[2];
-};
-
 #define R600_BLOCK_STATUS_ENABLED      (1 << 0)
 #define R600_BLOCK_STATUS_DIRTY                (1 << 1)
-#define R600_BLOCK_STATUS_RESOURCE_DIRTY       (1 << 2)
 
 struct r600_block_reloc {
        struct r600_resource    *bo;
@@ -188,8 +180,17 @@ struct r600_so_target {
        unsigned                so_index;
 };
 
-#define R600_CONTEXT_DRAW_PENDING      (1 << 0)
-#define R600_CONTEXT_DST_CACHES_DIRTY  (1 << 1)
+#define R600_CONTEXT_PS_PARTIAL_FLUSH          (1 << 0)
+#define R600_CONTEXT_CB_FLUSH                  (1 << 1)
+#define R600_CONTEXT_DB_FLUSH                  (1 << 2)
+#define R600_CONTEXT_SHADERCONST_FLUSH         (1 << 3)
+#define R600_CONTEXT_TEX_FLUSH                 (1 << 4)
+#define R600_CONTEXT_VTX_FLUSH                 (1 << 5)
+#define R600_CONTEXT_STREAMOUT_FLUSH           (1 << 6)
+#define R600_CONTEXT_WAIT_IDLE                 (1 << 7)
+#define R600_CONTEXT_FLUSH_AND_INV             (1 << 8)
+#define R600_CONTEXT_HTILE_ERRATA              (1 << 9)
+#define R600_CONTEXT_FLUSH_AND_INV_CB_META     (1 << 10)
 
 struct r600_context;
 struct r600_screen;
@@ -197,30 +198,21 @@ struct r600_screen;
 void r600_get_backend_mask(struct r600_context *ctx);
 int r600_context_init(struct r600_context *ctx);
 void r600_context_fini(struct r600_context *ctx);
+void r600_context_pipe_state_emit(struct r600_context *ctx, struct r600_pipe_state *state, unsigned pkt_flags);
 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid);
-void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
-void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 void r600_context_flush(struct r600_context *ctx, unsigned flags);
+void r600_begin_new_cs(struct r600_context *ctx);
 
 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
                              unsigned offset, unsigned value);
-void r600_inval_shader_cache(struct r600_context *ctx);
-void r600_inval_texture_cache(struct r600_context *ctx);
-void r600_inval_vertex_cache(struct r600_context *ctx);
-void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now);
+void r600_flush_emit(struct r600_context *ctx);
 
 void r600_context_streamout_begin(struct r600_context *ctx);
 void r600_context_streamout_end(struct r600_context *ctx);
-void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block, unsigned pkt_flags);
-void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 
 int evergreen_context_init(struct r600_context *ctx);
-void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
-void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 
 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
                                 struct r600_pipe_state *state,
@@ -234,19 +226,7 @@ void _r600_pipe_state_add_reg(struct r600_context *ctx,
                              uint32_t offset, uint32_t value,
                              uint32_t range_id, uint32_t block_id);
 
-void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
-                                    uint32_t offset, uint32_t value,
-                                    struct r600_resource *bo,
-                                    enum radeon_bo_usage usage);
-
 #define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
 #define r600_pipe_state_add_reg(state, offset, value) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset))
 
-static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
-                                          uint32_t value)
-{
-       state->regs[state->nregs].value = value;
-       state->nregs++;
-}
-
 #endif