* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <stdio.h>
-#include <errno.h>
-#include <byteswap.h>
-#include "util/u_format.h"
-#include "util/u_memory.h"
-#include "pipe/p_shader_tokens.h"
-#include "r600_pipe.h"
#include "r600_sq.h"
#include "r600_opcodes.h"
-#include "r600_asm.h"
#include "r600_formats.h"
#include "r600d.h"
+#include <errno.h>
+#include <byteswap.h>
+#include "util/u_memory.h"
+#include "pipe/p_shader_tokens.h"
+
#define NUM_OF_CYCLES 3
#define NUM_OF_COMPONENTS 4
return 0;
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
return 2;
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
return 1;
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
return 0;
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SUB_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_UINT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_UINT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
- case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
- case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
return 2;
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
return 1;
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
return tex;
}
-void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class)
+void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
{
+ if ((chip_class == R600) && (family != CHIP_RV670))
+ bc->ar_handling = AR_HANDLE_RV6XX;
+ else
+ bc->ar_handling = AR_HANDLE_NORMAL;
+
+ if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
+ family != CHIP_RS880))
+ bc->r6xx_nop_after_rel_dst = 1;
+ else
+ bc->r6xx_nop_after_rel_dst = 0;
LIST_INITHEAD(&bc->cf);
bc->chip_class = chip_class;
}
if (cf == NULL)
return -ENOMEM;
LIST_ADDTAIL(&cf->list, &bc->cf);
- if (bc->cf_last)
+ if (bc->cf_last) {
cf->id = bc->cf_last->id + 2;
+ if (bc->cf_last->eg_alu_extended) {
+ /* take into account extended alu size */
+ cf->id += 2;
+ bc->ndw += 2;
+ }
+ }
bc->cf_last = cf;
bc->ncf++;
bc->ndw += 2;
bc->force_add_cf = 0;
+ bc->ar_loaded = 0;
return 0;
}
{
int r;
+ if (output->gpr >= bc->ngpr)
+ bc->ngpr = output->gpr + 1;
+
if (bc->cf_last && (bc->cf_last->inst == output->inst ||
(bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
+ alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
+ alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
case EVERGREEN:
case CAYMAN:
default:
}
}
-/* alu instructions that can only execute on the vector unit */
-static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
{
- return is_alu_reduction_inst(bc, alu) ||
- is_alu_mova_inst(bc, alu) ||
- (bc->chip_class == EVERGREEN &&
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR);
+ return min <= opcode && opcode <= max;
}
-/* alu instructions that can only execute on the trans unit */
-static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+/* ALU instructions that can only execute on the vector unit:
+ *
+ * opcode ranges:
+ * R6xx/R7xx:
+ * op3 : [0x08 - 0x0B]
+ * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
+ *
+ * EVERGREEN:
+ * op3: [0x04 - 0x11]
+ * op2: [0xA0 - 0xE2]
+ */
+static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
{
switch (bc->chip_class) {
case R600:
case R700:
- if (!alu->is_op3)
- return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
+ if (alu->is_op3)
+ return is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
+ V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
else
- return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
- alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
- alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
- alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
+ return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
+
case EVERGREEN:
+ if (alu->is_op3)
+ return is_opcode_in_range(alu->inst,
+ EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
+ EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
+ else
+ return is_opcode_in_range(alu->inst,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
case CAYMAN:
default:
- if (!alu->is_op3)
- /* Note that FLT_TO_INT_* instructions are vector-only instructions
- * on Evergreen, despite what the documentation says. FLT_TO_INT
- * can do both vector and scalar. */
- return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
+ assert(0);
+ return 0;
+ }
+}
+
+/* ALU instructions that can only execute on the trans unit:
+ *
+ * opcode ranges:
+ * R600:
+ * op3: 0x0C
+ * op2: [0x60 - 0x79]
+ *
+ * R700:
+ * op3: 0x0C
+ * op2: [0x60 - 0x6F], [0x73 - 0x79]
+ *
+ * EVERGREEN:
+ * op3: 0x1F
+ * op2: [0x81 - 0x9C]
+ */
+static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+{
+
+ switch (bc->chip_class) {
+ case R600:
+ if (alu->is_op3)
+ return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
+ else
+ return is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
+ case R700:
+ if (alu->is_op3)
+ return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
else
+ return is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
+ case EVERGREEN:
+ if (alu->is_op3)
return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
+ else
+ return is_opcode_in_range(alu->inst,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
+ case CAYMAN:
+ default:
+ assert(0);
+ return 0;
}
}
!is_alu_trans_unit_inst(bc, alu);
}
+static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+{
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
+ return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
+ case EVERGREEN:
+ case CAYMAN:
+ default:
+ return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
+ }
+}
+
static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
struct r600_bytecode_alu *assignment[5])
{
return r;
}
} else if (is_cfile(sel)) {
- r = reserve_cfile(bc, bs, sel, elem);
+ r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
if (r)
return r;
}
const_count++;
}
if (is_cfile(sel)) {
- r = reserve_cfile(bc, bs, sel, elem);
+ r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
if (r)
return r;
}
return 0;
}
-void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
{
switch(value) {
case 0:
result[i] = prev[i];
result[4] = slots[i];
} else if (is_alu_any_unit_inst(bc, prev[i])) {
+ if (slots[i]->dst.sel == prev[i]->dst.sel &&
+ (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
+ (prev[i]->dst.write == 1 || prev[i]->is_op3))
+ return 0;
+
result[i] = slots[i];
result[4] = prev[i];
} else
return 0;
} else if(!slots[i]) {
continue;
- } else
+ } else {
+ if (max_slots == 5 && slots[i] && prev[4] &&
+ slots[i]->dst.sel == prev[4]->dst.sel &&
+ slots[i]->dst.chan == prev[4]->dst.chan &&
+ (slots[i]->dst.write == 1 || slots[i]->is_op3) &&
+ (prev[4]->dst.write == 1 || prev[4]->is_op3))
+ return 0;
+
result[i] = slots[i];
+ }
alu = slots[i];
num_once_inst += is_alu_once_inst(bc, alu);
+ /* don't reschedule NOPs */
+ if (is_nop_inst(bc, alu))
+ return 0;
+
/* Let's check dst gpr. */
if (alu->dst.rel) {
if (have_mova)
continue;
for (j = 0; j < max_slots; ++j) {
- if (!prev[j] || !prev[j]->dst.write)
+ if (!prev[j] || !(prev[j]->dst.write || prev[j]->is_op3))
continue;
/* If it's relative then we can't determin which gpr is really used. */
return 0;
}
-/* This code handles kcache lines as single blocks of 32 constants. We could
- * probably do slightly better by recognizing that we actually have two
- * consecutive lines of 16 constants, but the resulting code would also be
- * somewhat more complicated. */
-static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
+/* we'll keep kcache sets sorted by bank & addr */
+static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
+ struct r600_bytecode_kcache *kcache,
+ unsigned bank, unsigned line)
{
- struct r600_bytecode_kcache *kcache = bc->cf_last->kcache;
- unsigned int required_lines;
- unsigned int free_lines = 0;
- unsigned int cache_line[3];
- unsigned int count = 0;
- unsigned int i, j;
- int r;
+ int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
- /* Collect required cache lines. */
- for (i = 0; i < 3; ++i) {
- boolean found = false;
- unsigned int line;
+ for (i = 0; i < kcache_banks; i++) {
+ if (kcache[i].mode) {
+ int d;
- if (alu->src[i].sel < 512)
- continue;
+ if (kcache[i].bank < bank)
+ continue;
- line = ((alu->src[i].sel - 512) / 32) * 2;
+ if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
+ kcache[i].bank > bank) {
+ /* try to insert new line */
+ if (kcache[kcache_banks-1].mode) {
+ /* all sets are in use */
+ return -ENOMEM;
+ }
- for (j = 0; j < count; ++j) {
- if (cache_line[j] == line) {
- found = true;
- break;
+ memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
+ kcache[i].bank = bank;
+ kcache[i].addr = line;
+ return 0;
}
- }
- if (!found)
- cache_line[count++] = line;
+ d = line - kcache[i].addr;
+
+ if (d == -1) {
+ kcache[i].addr--;
+ if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
+ /* we are prepending the line to the current set,
+ * discarding the existing second line,
+ * so we'll have to insert line+2 after it */
+ line += 2;
+ continue;
+ } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
+ return 0;
+ } else {
+ /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
+ return -ENOMEM;
+ }
+ } else if (d == 1) {
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
+ return 0;
+ } else if (d == 0)
+ return 0;
+ } else { /* free kcache set - use it */
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
+ kcache[i].bank = bank;
+ kcache[i].addr = line;
+ return 0;
+ }
}
+ return -ENOMEM;
+}
+
+static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
+ struct r600_bytecode_kcache *kcache,
+ struct r600_bytecode_alu *alu)
+{
+ int i, r;
- /* This should never actually happen. */
- if (count >= 3) return -ENOMEM;
+ for (i = 0; i < 3; i++) {
+ unsigned bank, line, sel = alu->src[i].sel;
- for (i = 0; i < 2; ++i) {
- if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
- ++free_lines;
- }
+ if (sel < 512)
+ continue;
+
+ bank = alu->src[i].kc_bank;
+ line = (sel-512)>>4;
+
+ if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
+ return r;
}
+ return 0;
+}
- /* Filter lines pulled in by previous intructions. Note that this is
- * only for the required_lines count, we can't remove these from the
- * cache_line array since we may have to start a new ALU clause. */
- for (i = 0, required_lines = count; i < count; ++i) {
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
- kcache[j].addr == cache_line[i]) {
- --required_lines;
- break;
+static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
+ struct r600_bytecode_alu *alu,
+ struct r600_bytecode_kcache * kcache)
+{
+ int i, j;
+
+ /* Alter the src operands to refer to the kcache. */
+ for (i = 0; i < 3; ++i) {
+ static const unsigned int base[] = {128, 160, 256, 288};
+ unsigned int line, sel = alu->src[i].sel, found = 0;
+
+ if (sel < 512)
+ continue;
+
+ sel -= 512;
+ line = sel>>4;
+
+ for (j = 0; j < 4 && !found; ++j) {
+ switch (kcache[j].mode) {
+ case V_SQ_CF_KCACHE_NOP:
+ case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
+ R600_ERR("unexpected kcache line mode\n");
+ return -ENOMEM;
+ default:
+ if (kcache[j].bank == alu->src[i].kc_bank &&
+ kcache[j].addr <= line &&
+ line < kcache[j].addr + kcache[j].mode) {
+ alu->src[i].sel = sel - (kcache[j].addr<<4);
+ alu->src[i].sel += base[j];
+ found=1;
+ }
}
}
}
+ return 0;
+}
+
+static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
+{
+ struct r600_bytecode_kcache kcache_sets[4];
+ struct r600_bytecode_kcache *kcache = kcache_sets;
+ int r;
- /* Start a new ALU clause if needed. */
- if (required_lines > free_lines) {
+ memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
+
+ if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
+ /* can't alloc, need to start new clause */
if ((r = r600_bytecode_add_cf(bc))) {
return r;
}
- bc->cf_last->inst = (type << 3);
+ bc->cf_last->inst = type;
+
+ /* retry with the new clause */
kcache = bc->cf_last->kcache;
+ if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
+ /* can't alloc again- should never happen */
+ return r;
+ }
+ } else {
+ /* update kcache sets */
+ memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
}
- /* Setup the kcache lines. */
- for (i = 0; i < count; ++i) {
- boolean found = false;
+ /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
+ if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
+ if (bc->chip_class < EVERGREEN)
+ return -ENOMEM;
+ bc->cf_last->eg_alu_extended = 1;
+ }
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
- kcache[j].addr == cache_line[i]) {
- found = true;
- break;
- }
- }
+ return 0;
+}
- if (found) continue;
+static int insert_nop_r6xx(struct r600_bytecode *bc)
+{
+ struct r600_bytecode_alu alu;
+ int r, i;
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
- kcache[j].bank = 0;
- kcache[j].addr = cache_line[i];
- kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
- break;
- }
- }
+ for (i = 0; i < 4; i++) {
+ memset(&alu, 0, sizeof(alu));
+ alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+ alu.src[0].chan = i;
+ alu.dst.chan = i;
+ alu.last = (i == 3);
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
}
+ return 0;
+}
- /* Alter the src operands to refer to the kcache. */
- for (i = 0; i < 3; ++i) {
- static const unsigned int base[] = {128, 160, 256, 288};
- unsigned int line;
+/* load AR register from gpr (bc->ar_reg) with MOVA_INT */
+static int load_ar_r6xx(struct r600_bytecode *bc)
+{
+ struct r600_bytecode_alu alu;
+ int r;
- if (alu->src[i].sel < 512)
- continue;
+ if (bc->ar_loaded)
+ return 0;
- alu->src[i].sel -= 512;
- line = (alu->src[i].sel / 32) * 2;
+ /* hack to avoid making MOVA the last instruction in the clause */
+ if ((bc->cf_last->ndw>>1) >= 110)
+ bc->force_add_cf = 1;
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
- kcache[j].addr == line) {
- alu->src[i].sel &= 0x1f;
- alu->src[i].sel += base[j];
- break;
- }
- }
- }
+ memset(&alu, 0, sizeof(alu));
+ alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
+ alu.src[0].sel = bc->ar_reg;
+ alu.last = 1;
+ alu.index_mode = INDEX_MODE_LOOP;
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
+ /* no requirement to set uses waterfall on MOVA_GPR_INT */
+ bc->ar_loaded = 1;
+ return 0;
+}
+
+/* load AR register from gpr (bc->ar_reg) with MOVA_INT */
+static int load_ar(struct r600_bytecode *bc)
+{
+ struct r600_bytecode_alu alu;
+ int r;
+
+ if (bc->ar_handling)
+ return load_ar_r6xx(bc);
+
+ if (bc->ar_loaded)
+ return 0;
+
+ /* hack to avoid making MOVA the last instruction in the clause */
+ if ((bc->cf_last->ndw>>1) >= 110)
+ bc->force_add_cf = 1;
+
+ memset(&alu, 0, sizeof(alu));
+ alu.inst = BC_INST(bc, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
+ alu.src[0].sel = bc->ar_reg;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
+
+ bc->cf_last->r6xx_uses_waterfall = 1;
+ bc->ar_loaded = 1;
return 0;
}
return -ENOMEM;
memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
- if (bc->cf_last != NULL && bc->cf_last->inst != (type << 3)) {
+ if (bc->cf_last != NULL && bc->cf_last->inst != type) {
/* check if we could add it anyway */
- if (bc->cf_last->inst == (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) &&
- type == V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE) {
+ if (bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) &&
+ type == BC_INST(bc, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE)) {
LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
if (lalu->predicate) {
bc->force_add_cf = 1;
return r;
}
}
- bc->cf_last->inst = (type << 3);
+ bc->cf_last->inst = type;
+
+ /* Check AR usage and load it if required */
+ for (i = 0; i < 3; i++)
+ if (nalu->src[i].rel && !bc->ar_loaded)
+ load_ar(bc);
+
+ if (nalu->dst.rel && !bc->ar_loaded)
+ load_ar(bc);
/* Setup the kcache for this ALU instruction. This will start a new
* ALU clause if needed. */
bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
bc->cf_last->curr_bs_head = NULL;
}
+
+ if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
+ insert_nop_r6xx(bc);
+
return 0;
}
return 8;
case R700:
- return 16;
-
case EVERGREEN:
case CAYMAN:
- return 64;
+ return 16;
default:
R600_ERR("Unknown chip class %d.\n", bc->chip_class);
}
}
-static inline boolean last_inst_was_vtx_fetch(struct r600_bytecode *bc)
+static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
{
- if (bc->chip_class == CAYMAN) {
- if (bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC)
- return TRUE;
- } else {
- if (bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
- bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC)
- return TRUE;
+ switch (bc->chip_class) {
+ case R700:
+ case R600:
+ return bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
+ bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC;
+ case EVERGREEN:
+ return bc->cf_last->inst != EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
+ case CAYMAN:
+ return bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
+ default:
+ R600_ERR("Unknown chip class %d.\n", bc->chip_class);
+ return FALSE;
}
- return FALSE;
}
int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
/* cf can contains only alu or only vtx or only tex */
if (bc->cf_last == NULL ||
- last_inst_was_vtx_fetch(bc) ||
+ last_inst_was_not_vtx_fetch(bc) ||
bc->force_add_cf) {
r = r600_bytecode_add_cf(bc);
if (r) {
free(nvtx);
return r;
}
- if (bc->chip_class == CAYMAN)
- bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
- else
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
+ break;
+ case EVERGREEN:
+ bc->cf_last->inst = EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX;
+ break;
+ case CAYMAN:
+ bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
+ break;
+ default:
+ R600_ERR("Unknown chip class %d.\n", bc->chip_class);
+ return -EINVAL;
+ }
}
LIST_ADDTAIL(&nvtx->list, &bc->cf_last->vtx);
/* each fetch use 4 dwords */
bc->ndw += 4;
if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
bc->force_add_cf = 1;
+
+ bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
+ bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
+
return 0;
}
/* we can't fetch data und use it as texture lookup address in the same TEX clause */
if (bc->cf_last != NULL &&
- bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
+ bc->cf_last->inst == BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX)) {
struct r600_bytecode_tex *ttex;
LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
if (ttex->dst_gpr == ntex->src_gpr) {
/* cf can contains only alu or only vtx or only tex */
if (bc->cf_last == NULL ||
- bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
+ bc->cf_last->inst != BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX) ||
bc->force_add_cf) {
r = r600_bytecode_add_cf(bc);
if (r) {
free(ntex);
return r;
}
- bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_TEX;
+ bc->cf_last->inst = BC_INST(bc, V_SQ_CF_WORD1_SQ_CF_INST_TEX);
}
if (ntex->src_gpr >= bc->ngpr) {
bc->ngpr = ntex->src_gpr + 1;
S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
+ S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
S_SQ_ALU_WORD0_LAST(alu->last);
if (alu->is_op3) {
static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
{
*bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
- *bytecode++ = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+ *bytecode++ = cf->inst |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1);
}
unsigned id = cf->id;
switch (cf->inst) {
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
- bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
+ bc->bytecode[id++] = cf->inst |
S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
- S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
+ cf->output.inst |
S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
break;
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
+ bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
+ S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
+ S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
+ S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type);
+ bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
+ S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
+ cf->output.inst |
+ S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program) |
+ S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
+ S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
+ break;
case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
case V_SQ_CF_WORD1_SQ_CF_INST_POP:
case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
- bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+ bc->bytecode[id++] = cf->inst |
S_SQ_CF_WORD1_BARRIER(1) |
S_SQ_CF_WORD1_COND(cf->cond) |
S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
/* addr start after all the CF instructions */
addr = bc->cf_last->id + 2;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
- switch (cf->inst) {
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
- break;
- case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
- /* fetch node need to be 16 bytes aligned*/
- addr += 3;
- addr &= 0xFFFFFFFCUL;
- break;
- case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
- case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
- case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
- case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
- break;
- case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
- case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
- case V_SQ_CF_WORD1_SQ_CF_INST_POP:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
- case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
- case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
- case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
- break;
- default:
- R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
- return -EINVAL;
+ if (bc->chip_class >= EVERGREEN) {
+ switch (cf->inst) {
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ /* fetch node need to be 16 bytes aligned*/
+ addr += 3;
+ addr &= 0xFFFFFFFCUL;
+ break;
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+ case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
+ case CF_NATIVE:
+ break;
+ default:
+ R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
+ return -EINVAL;
+ }
+ } else {
+ switch (cf->inst) {
+ case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+ /* fetch node need to be 16 bytes aligned*/
+ addr += 3;
+ addr &= 0xFFFFFFFCUL;
+ break;
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
+ case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+ case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+ break;
+ default:
+ R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
+ return -EINVAL;
+ }
}
cf->addr = addr;
addr += cf->ndw;
return -ENOMEM;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
addr = cf->addr;
- if (bc->chip_class >= EVERGREEN)
+ if (bc->chip_class >= EVERGREEN) {
r = eg_bytecode_cf_build(bc, cf);
- else
- r = r600_bytecode_cf_build(bc, cf);
- if (r)
- return r;
- switch (cf->inst) {
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
- nliteral = 0;
- memset(literal, 0, sizeof(literal));
- LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
- r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
- if (r)
- return r;
- r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
- switch(bc->chip_class) {
- case R600:
- r = r600_bytecode_alu_build(bc, alu, addr);
- break;
- case R700:
- case EVERGREEN: /* eg alu is same encoding as r700 */
- case CAYMAN: /* eg alu is same encoding as r700 */
- r = r700_bytecode_alu_build(bc, alu, addr);
- break;
- default:
- R600_ERR("unknown chip class %d.\n", bc->chip_class);
- return -EINVAL;
- }
- if (r)
- return r;
- addr += 2;
- if (alu->last) {
- for (i = 0; i < align(nliteral, 2); ++i) {
- bc->bytecode[addr++] = literal[i];
+ if (r)
+ return r;
+
+ switch (cf->inst) {
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ nliteral = 0;
+ memset(literal, 0, sizeof(literal));
+ LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
+ r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
+ if (r)
+ return r;
+ r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
+ r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
+
+ switch(bc->chip_class) {
+ case EVERGREEN: /* eg alu is same encoding as r700 */
+ case CAYMAN:
+ r = r700_bytecode_alu_build(bc, alu, addr);
+ break;
+ default:
+ R600_ERR("unknown chip class %d.\n", bc->chip_class);
+ return -EINVAL;
+ }
+ if (r)
+ return r;
+ addr += 2;
+ if (alu->last) {
+ for (i = 0; i < align(nliteral, 2); ++i) {
+ bc->bytecode[addr++] = literal[i];
+ }
+ nliteral = 0;
+ memset(literal, 0, sizeof(literal));
}
- nliteral = 0;
- memset(literal, 0, sizeof(literal));
}
- }
- break;
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
- LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
- r = r600_bytecode_vtx_build(bc, vtx, addr);
- if (r)
- return r;
- addr += 4;
- }
- break;
- case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
- if (bc->chip_class == CAYMAN) {
+ break;
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
r = r600_bytecode_vtx_build(bc, vtx, addr);
if (r)
return r;
addr += 4;
}
+ break;
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+ LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+ assert(bc->chip_class >= EVERGREEN);
+ r = r600_bytecode_vtx_build(bc, vtx, addr);
+ if (r)
+ return r;
+ addr += 4;
+ }
+ LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
+ r = r600_bytecode_tex_build(bc, tex, addr);
+ if (r)
+ return r;
+ addr += 4;
+ }
+ break;
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+ case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
+ break;
+ case CF_NATIVE:
+ break;
+ default:
+ R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
+ return -EINVAL;
}
- LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
- r = r600_bytecode_tex_build(bc, tex, addr);
- if (r)
- return r;
- addr += 4;
+ } else {
+ r = r600_bytecode_cf_build(bc, cf);
+ if (r)
+ return r;
+
+ switch (cf->inst) {
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ nliteral = 0;
+ memset(literal, 0, sizeof(literal));
+ LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
+ r = r600_bytecode_alu_nliterals(bc, alu, literal, &nliteral);
+ if (r)
+ return r;
+ r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
+ r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
+
+ switch(bc->chip_class) {
+ case R600:
+ r = r600_bytecode_alu_build(bc, alu, addr);
+ break;
+ case R700:
+ r = r700_bytecode_alu_build(bc, alu, addr);
+ break;
+ default:
+ R600_ERR("unknown chip class %d.\n", bc->chip_class);
+ return -EINVAL;
+ }
+ if (r)
+ return r;
+ addr += 2;
+ if (alu->last) {
+ for (i = 0; i < align(nliteral, 2); ++i) {
+ bc->bytecode[addr++] = literal[i];
+ }
+ nliteral = 0;
+ memset(literal, 0, sizeof(literal));
+ }
+ }
+ break;
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+ LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+ r = r600_bytecode_vtx_build(bc, vtx, addr);
+ if (r)
+ return r;
+ addr += 4;
+ }
+ break;
+ case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+ LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
+ r = r600_bytecode_tex_build(bc, tex, addr);
+ if (r)
+ return r;
+ addr += 4;
+ }
+ break;
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+ case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+ break;
+ default:
+ R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
+ return -EINVAL;
}
- break;
- case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
- case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
- case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
- case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
- case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
- case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
- case V_SQ_CF_WORD1_SQ_CF_INST_POP:
- case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
- case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
- case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
- break;
- default:
- R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
- return -EINVAL;
}
}
return 0;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
id = cf->id;
- switch (cf->inst) {
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER << 3):
- case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
- fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
- fprintf(stderr, "ADDR:%d ", cf->addr);
- fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
- fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
- fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
- id++;
- fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
- fprintf(stderr, "INST:%d ", cf->inst);
- fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
- fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
- fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
- fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
- break;
- case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
- case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
- fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
- fprintf(stderr, "ADDR:%d\n", cf->addr);
- id++;
- fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
- fprintf(stderr, "INST:%d ", cf->inst);
- fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
- break;
- case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
- case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
- case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
- case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
- fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
- fprintf(stderr, "GPR:%X ", cf->output.gpr);
- fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
- fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
- fprintf(stderr, "TYPE:%X\n", cf->output.type);
- id++;
- fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
- fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
- fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
- fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
- fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
- fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
- fprintf(stderr, "INST:%d ", cf->output.inst);
- fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
- fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
- break;
- case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
- case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
- case V_SQ_CF_WORD1_SQ_CF_INST_POP:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
- case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
- case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
- case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
- case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
- fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
- fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
- id++;
- fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
- fprintf(stderr, "INST:%d ", cf->inst);
- fprintf(stderr, "COND:%X ", cf->cond);
- fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
- break;
+ if (bc->chip_class >= EVERGREEN) {
+ switch (cf->inst) {
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+ case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ if (cf->eg_alu_extended) {
+ fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
+ fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
+ fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
+ fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
+ id++;
+ fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
+ fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
+ fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
+ fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
+ id++;
+ }
+
+ fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
+ fprintf(stderr, "ADDR:%d ", cf->addr);
+ fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
+ fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
+ fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
+ id++;
+ fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
+ fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
+ fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
+ fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
+ fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
+ fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
+ break;
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
+ fprintf(stderr, "ADDR:%d\n", cf->addr);
+ id++;
+ fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
+ fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
+ fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
+ break;
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+ fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
+ fprintf(stderr, "GPR:%X ", cf->output.gpr);
+ fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
+ fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
+ fprintf(stderr, "TYPE:%X\n", cf->output.type);
+ id++;
+ fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
+ fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
+ fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
+ fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
+ fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
+ fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
+ fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
+ fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
+ fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
+ break;
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2_BUF3:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF0:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF1:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF2:
+ case EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3_BUF3:
+ fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
+ (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
+ EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
+ (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
+ EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
+ fprintf(stderr, "GPR:%X ", cf->output.gpr);
+ fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
+ fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
+ fprintf(stderr, "TYPE:%X\n", cf->output.type);
+ id++;
+ fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i_BUF%i ", id, bc->bytecode[id],
+ (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
+ EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) / 4,
+ (EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
+ EG_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0_BUF0)) % 4);
+ fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
+ fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
+ fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
+ fprintf(stderr, "INST:%d ", cf->output.inst);
+ fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
+ fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
+ break;
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+ case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
+ fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
+ fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
+ id++;
+ fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
+ fprintf(stderr, "INST:0x%x ", EG_G_SQ_CF_WORD1_CF_INST(cf->inst));
+ fprintf(stderr, "COND:%X ", cf->cond);
+ fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
+ break;
+ case CF_NATIVE:
+ fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
+ fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
+ break;
+ default:
+ R600_ERR("Unknown instruction %0x\n", cf->inst);
+ }
+ } else {
+ switch (cf->inst) {
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
+ case V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
+ fprintf(stderr, "ADDR:%d ", cf->addr);
+ fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
+ fprintf(stderr, "KCACHE_BANK0:%X ", cf->kcache[0].bank);
+ fprintf(stderr, "KCACHE_BANK1:%X\n", cf->kcache[1].bank);
+ id++;
+ fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
+ fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALU_WORD1_CF_INST(cf->inst));
+ fprintf(stderr, "KCACHE_MODE1:%X ", cf->kcache[1].mode);
+ fprintf(stderr, "KCACHE_ADDR0:%X ", cf->kcache[0].addr);
+ fprintf(stderr, "KCACHE_ADDR1:%X ", cf->kcache[1].addr);
+ fprintf(stderr, "COUNT:%d\n", cf->ndw / 2);
+ break;
+ case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
+ case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
+ fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
+ fprintf(stderr, "ADDR:%d\n", cf->addr);
+ id++;
+ fprintf(stderr, "%04d %08X TEX/VTX ", id, bc->bytecode[id]);
+ fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
+ fprintf(stderr, "COUNT:%d\n", cf->ndw / 4);
+ break;
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+ fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
+ fprintf(stderr, "GPR:%X ", cf->output.gpr);
+ fprintf(stderr, "ELEM_SIZE:%X ", cf->output.elem_size);
+ fprintf(stderr, "ARRAY_BASE:%X ", cf->output.array_base);
+ fprintf(stderr, "TYPE:%X\n", cf->output.type);
+ id++;
+ fprintf(stderr, "%04d %08X EXPORT ", id, bc->bytecode[id]);
+ fprintf(stderr, "SWIZ_X:%X ", cf->output.swizzle_x);
+ fprintf(stderr, "SWIZ_Y:%X ", cf->output.swizzle_y);
+ fprintf(stderr, "SWIZ_Z:%X ", cf->output.swizzle_z);
+ fprintf(stderr, "SWIZ_W:%X ", cf->output.swizzle_w);
+ fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
+ fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst));
+ fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
+ fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
+ break;
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM1:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM2:
+ case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM3:
+ fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
+ R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
+ R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
+ fprintf(stderr, "GPR:%X ", cf->output.gpr);
+ fprintf(stderr, "ELEM_SIZE:%i ", cf->output.elem_size);
+ fprintf(stderr, "ARRAY_BASE:%i ", cf->output.array_base);
+ fprintf(stderr, "TYPE:%X\n", cf->output.type);
+ id++;
+ fprintf(stderr, "%04d %08X EXPORT MEM_STREAM%i ", id, bc->bytecode[id],
+ R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->inst) -
+ R600_G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_STREAM0));
+ fprintf(stderr, "ARRAY_SIZE:%i ", cf->output.array_size);
+ fprintf(stderr, "COMP_MASK:%X ", cf->output.comp_mask);
+ fprintf(stderr, "BARRIER:%X ", cf->output.barrier);
+ fprintf(stderr, "INST:%d ", cf->output.inst);
+ fprintf(stderr, "BURST_COUNT:%d ", cf->output.burst_count);
+ fprintf(stderr, "EOP:%X\n", cf->output.end_of_program);
+ break;
+ case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+ case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+ case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
+ case V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
+ case V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
+ fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
+ fprintf(stderr, "ADDR:%d\n", cf->cf_addr);
+ id++;
+ fprintf(stderr, "%04d %08X CF ", id, bc->bytecode[id]);
+ fprintf(stderr, "INST:0x%x ", R600_G_SQ_CF_WORD1_CF_INST(cf->inst));
+ fprintf(stderr, "COND:%X ", cf->cond);
+ fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
+ break;
+ default:
+ R600_ERR("Unknown instruction %0x\n", cf->inst);
+ }
}
id = cf->addr;
fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
fprintf(stderr, "REL:%d ", alu->src[1].rel);
fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
- fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
+ fprintf(stderr, "NEG:%d ", alu->src[1].neg);
+ fprintf(stderr, "IM:%d) ", alu->index_mode);
fprintf(stderr, "LAST:%d)\n", alu->last);
id++;
fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
- fprintf(stderr, "INST:%d ", alu->inst);
+ fprintf(stderr, "INST:0x%x ", alu->inst);
fprintf(stderr, "DST(SEL:%d ", alu->dst.sel);
fprintf(stderr, "CHAN:%d ", alu->dst.chan);
fprintf(stderr, "REL:%d ", alu->dst.rel);
if (alu->last) {
for (i = 0; i < nliteral; i++, id++) {
float *f = (float*)(bc->bytecode + id);
- fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
+ fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
+ *(bc->bytecode + id));
}
id += nliteral & 1;
nliteral = 0;
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
- fprintf(stderr, "INST:%d ", tex->inst);
+ fprintf(stderr, "INST:0x%x ", tex->inst);
fprintf(stderr, "RESOURCE_ID:%d ", tex->resource_id);
fprintf(stderr, "SRC(GPR:%d ", tex->src_gpr);
fprintf(stderr, "REL:%d)\n", tex->src_rel);
fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
fprintf(stderr, "ENDIAN:%d ", vtx->endian);
fprintf(stderr, "OFFSET:%d\n", vtx->offset);
- /* TODO */
+ /* XXX */
id++;
fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
id++;
fprintf(stderr, "--------------------------------------\n");
}
-static void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
- unsigned *num_format, unsigned *format_comp, unsigned *endian)
+static void r600_vertex_data_type(enum pipe_format pformat,
+ unsigned *format,
+ unsigned *num_format, unsigned *format_comp, unsigned *endian)
{
const struct util_format_description *desc;
unsigned i;
if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
*format_comp = 1;
}
- if (desc->channel[i].normalized) {
- *num_format = 0;
- } else {
- *num_format = 2;
+
+ *num_format = 0;
+ if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
+ desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+ if (!desc->channel[i].normalized) {
+ if (desc->channel[i].pure_integer)
+ *num_format = 1;
+ else
+ *num_format = 2;
+ }
}
return;
out_unknown:
R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
}
-int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
+int r600_vertex_elements_build_fetch_shader(struct r600_context *rctx, struct r600_vertex_element *ve)
{
static int dump_shaders = -1;
const struct util_format_description *desc;
unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
unsigned format, num_format, format_comp, endian;
- u32 *bytecode;
+ uint32_t *bytecode;
int i, r;
- /* Vertex element offsets need special handling. If the offset is
- * bigger than what we can put in the fetch instruction we need to
- * alter the vertex resource offset. In order to simplify code we
- * will bind one resource per element in such cases. It's a worst
- * case scenario. */
- for (i = 0; i < ve->count; i++) {
- ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
- if (ve->vbuffer_offset[i]) {
- ve->vbuffer_need_offset = 1;
- }
- }
-
memset(&bc, 0, sizeof(bc));
- r600_bytecode_init(&bc, rctx->chip_class);
+ r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
for (i = 0; i < ve->count; i++) {
if (elements[i].instance_divisor > 1) {
}
for (i = 0; i < ve->count; i++) {
- unsigned vbuffer_index;
- r600_vertex_data_type(ve->elements[i].src_format, &format, &num_format, &format_comp, &endian);
+ r600_vertex_data_type(ve->elements[i].src_format,
+ &format, &num_format, &format_comp, &endian);
+
desc = util_format_description(ve->elements[i].src_format);
if (desc == NULL) {
r600_bytecode_clear(&bc);
return -EINVAL;
}
- /* see above for vbuffer_need_offset explanation */
- vbuffer_index = elements[i].vertex_buffer_index;
+ if (elements[i].src_offset > 65535) {
+ r600_bytecode_clear(&bc);
+ R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
+ return -EINVAL;
+ }
+
memset(&vtx, 0, sizeof(vtx));
- vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
+ vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
ve->fs_size = bc.ndw*4;
- /* use PIPE_BIND_VERTEX_BUFFER so we use the cache buffer manager */
- ve->fetch_shader = r600_bo(rctx->radeon, ve->fs_size, 256, PIPE_BIND_VERTEX_BUFFER, PIPE_USAGE_IMMUTABLE);
+ ve->fetch_shader = (struct r600_resource*)
+ pipe_buffer_create(rctx->context.screen,
+ PIPE_BIND_CUSTOM,
+ PIPE_USAGE_IMMUTABLE, ve->fs_size);
if (ve->fetch_shader == NULL) {
r600_bytecode_clear(&bc);
return -ENOMEM;
}
- bytecode = r600_bo_map(rctx->radeon, ve->fetch_shader, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
+ bytecode = rctx->ws->buffer_map(ve->fetch_shader->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
if (bytecode == NULL) {
r600_bytecode_clear(&bc);
- r600_bo_reference(&ve->fetch_shader, NULL);
+ pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
return -ENOMEM;
}
memcpy(bytecode, bc.bytecode, ve->fs_size);
}
- r600_bo_unmap(rctx->radeon, ve->fetch_shader);
+ rctx->ws->buffer_unmap(ve->fetch_shader->cs_buf);
r600_bytecode_clear(&bc);
if (rctx->chip_class >= EVERGREEN)
projects / mesa.git / blobdiff