* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <stdio.h>
-#include <errno.h>
-#include <byteswap.h>
-#include "util/u_format.h"
-#include "util/u_memory.h"
-#include "pipe/p_shader_tokens.h"
-#include "r600_pipe.h"
#include "r600_sq.h"
#include "r600_opcodes.h"
-#include "r600_asm.h"
#include "r600_formats.h"
#include "r600d.h"
+#include <errno.h>
+#include <byteswap.h>
+#include "util/u_memory.h"
+#include "pipe/p_shader_tokens.h"
+
#define NUM_OF_CYCLES 3
#define NUM_OF_COMPONENTS 4
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
return 2;
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
+ case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
- case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY:
- case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_XY:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_ZW:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_XOR_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT:
return 2;
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT:
- case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_LOAD_P0:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P0:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT:
+ case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT:
return 1;
default: R600_ERR(
"Need instruction operand number for 0x%x.\n", alu->inst);
return tex;
}
-void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class)
+void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family)
{
+ if ((chip_class == R600) && (family != CHIP_RV670))
+ bc->ar_handling = AR_HANDLE_RV6XX;
+ else
+ bc->ar_handling = AR_HANDLE_NORMAL;
+
+ if ((chip_class == R600) && (family != CHIP_RV670 && family != CHIP_RS780 &&
+ family != CHIP_RS880))
+ bc->r6xx_nop_after_rel_dst = 1;
+ else
+ bc->r6xx_nop_after_rel_dst = 0;
LIST_INITHEAD(&bc->cf);
bc->chip_class = chip_class;
}
if (cf == NULL)
return -ENOMEM;
LIST_ADDTAIL(&cf->list, &bc->cf);
- if (bc->cf_last)
+ if (bc->cf_last) {
cf->id = bc->cf_last->id + 2;
+ if (bc->cf_last->eg_alu_extended) {
+ /* take into account extended alu size */
+ cf->id += 2;
+ bc->ndw += 2;
+ }
+ }
bc->cf_last = cf;
bc->ncf++;
bc->ndw += 2;
{
int r;
+ if (output->gpr >= bc->ngpr)
+ bc->ngpr = output->gpr + 1;
+
if (bc->cf_last && (bc->cf_last->inst == output->inst ||
(bc->cf_last->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT) &&
output->inst == BC_INST(bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE))) &&
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
+ alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT ||
+ alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT);
case EVERGREEN:
case CAYMAN:
default:
}
}
-/* alu instructions that can only execute on the vector unit */
+static int is_opcode_in_range(unsigned opcode, unsigned min, unsigned max)
+{
+ return min <= opcode && opcode <= max;
+}
+
+/* ALU instructions that can only execute on the vector unit:
+ *
+ * opcode ranges:
+ * R6xx/R7xx:
+ * op3 : [0x08 - 0x0B]
+ * op2 : 0x07, [0x15 - 0x18], [0x1B - 0x1D], [0x50 - 0x53], [0x7A - 0x7E]
+ *
+ * EVERGREEN:
+ * op3: [0x04 - 0x11]
+ * op2: [0xA0 - 0xE2]
+ */
static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
{
switch (bc->chip_class) {
case R600:
case R700:
- return is_alu_reduction_inst(bc, alu) ||
- is_alu_mova_inst(bc, alu);
+ if (alu->is_op3)
+ return is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64,
+ V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD_64_D2);
+ else
+ return (alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FREXP_64) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_64,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT32_TO_FLT64) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LDEXP_64,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETGE_64);
+
case EVERGREEN:
+ if (alu->is_op3)
+ return is_opcode_in_range(alu->inst,
+ EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_BFE_UINT,
+ EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_LDS_IDX_OP);
+ else
+ return is_opcode_in_range(alu->inst,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_BFM_INT,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INTERP_LOAD_P20);
case CAYMAN:
default:
- return is_alu_reduction_inst(bc, alu) ||
- is_alu_mova_inst(bc, alu) ||
- (alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW);
+ assert(0);
+ return 0;
}
}
-/* alu instructions that can only execute on the trans unit */
+/* ALU instructions that can only execute on the trans unit:
+ *
+ * opcode ranges:
+ * R600:
+ * op3: 0x0C
+ * op2: [0x60 - 0x79]
+ *
+ * R700:
+ * op3: 0x0C
+ * op2: [0x60 - 0x6F], [0x73 - 0x79]
+ *
+ * EVERGREEN:
+ * op3: 0x1F
+ * op2: [0x81 - 0x9C]
+ */
static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
{
+
switch (bc->chip_class) {
case R600:
+ if (alu->is_op3)
+ return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
+ else
+ return is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
case R700:
- if (!alu->is_op3)
- return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
- alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
+ if (alu->is_op3)
+ return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
else
- return alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT ||
- alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
- alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
- alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
+ return is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS) ||
+ is_opcode_in_range(alu->inst,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT,
+ V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT);
case EVERGREEN:
+ if (alu->is_op3)
+ return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
+ else
+ return is_opcode_in_range(alu->inst,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE,
+ EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT);
case CAYMAN:
default:
- if (!alu->is_op3)
- /* Note that FLT_TO_INT_* instructions are vector-only instructions
- * on Evergreen, despite what the documentation says. FLT_TO_INT
- * can do both vector and scalar. */
- return alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_UINT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_INT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_UINT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_FF ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_FF ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN ||
- alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_IEEE;
- else
- return alu->inst == EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
+ assert(0);
+ return 0;
}
}
!is_alu_trans_unit_inst(bc, alu);
}
+static int is_nop_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
+{
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
+ return (!alu->is_op3 && alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
+ case EVERGREEN:
+ case CAYMAN:
+ default:
+ return (!alu->is_op3 && alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
+ }
+}
+
static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
struct r600_bytecode_alu *assignment[5])
{
return r;
}
} else if (is_cfile(sel)) {
- r = reserve_cfile(bc, bs, sel, elem);
+ r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
if (r)
return r;
}
const_count++;
}
if (is_cfile(sel)) {
- r = reserve_cfile(bc, bs, sel, elem);
+ r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
if (r)
return r;
}
return 0;
}
-void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
{
switch(value) {
case 0:
alu = slots[i];
num_once_inst += is_alu_once_inst(bc, alu);
+ /* don't reschedule NOPs */
+ if (is_nop_inst(bc, alu))
+ return 0;
+
/* Let's check dst gpr. */
if (alu->dst.rel) {
if (have_mova)
return 0;
}
-/* This code handles kcache lines as single blocks of 32 constants. We could
- * probably do slightly better by recognizing that we actually have two
- * consecutive lines of 16 constants, but the resulting code would also be
- * somewhat more complicated. */
-static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
+/* we'll keep kcache sets sorted by bank & addr */
+static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
+ struct r600_bytecode_kcache *kcache,
+ unsigned bank, unsigned line)
{
- struct r600_bytecode_kcache *kcache = bc->cf_last->kcache;
- unsigned int required_lines;
- unsigned int free_lines = 0;
- unsigned int cache_line[3];
- unsigned int count = 0;
- unsigned int i, j;
- int r;
+ int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
- /* Collect required cache lines. */
- for (i = 0; i < 3; ++i) {
- boolean found = false;
- unsigned int line;
+ for (i = 0; i < kcache_banks; i++) {
+ if (kcache[i].mode) {
+ int d;
- if (alu->src[i].sel < 512)
- continue;
+ if (kcache[i].bank < bank)
+ continue;
- line = ((alu->src[i].sel - 512) / 32) * 2;
+ if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
+ kcache[i].bank > bank) {
+ /* try to insert new line */
+ if (kcache[kcache_banks-1].mode) {
+ /* all sets are in use */
+ return -ENOMEM;
+ }
- for (j = 0; j < count; ++j) {
- if (cache_line[j] == line) {
- found = true;
- break;
+ memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
+ kcache[i].bank = bank;
+ kcache[i].addr = line;
+ return 0;
}
- }
- if (!found)
- cache_line[count++] = line;
+ d = line - kcache[i].addr;
+
+ if (d == -1) {
+ kcache[i].addr--;
+ if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
+ /* we are prepending the line to the current set,
+ * discarding the existing second line,
+ * so we'll have to insert line+2 after it */
+ line += 2;
+ continue;
+ } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
+ return 0;
+ } else {
+ /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
+ return -ENOMEM;
+ }
+ } else if (d == 1) {
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
+ return 0;
+ } else if (d == 0)
+ return 0;
+ } else { /* free kcache set - use it */
+ kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
+ kcache[i].bank = bank;
+ kcache[i].addr = line;
+ return 0;
+ }
}
+ return -ENOMEM;
+}
+
+static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
+ struct r600_bytecode_kcache *kcache,
+ struct r600_bytecode_alu *alu)
+{
+ int i, r;
- /* This should never actually happen. */
- if (count >= 3) return -ENOMEM;
+ for (i = 0; i < 3; i++) {
+ unsigned bank, line, sel = alu->src[i].sel;
- for (i = 0; i < 2; ++i) {
- if (kcache[i].mode == V_SQ_CF_KCACHE_NOP) {
- ++free_lines;
- }
+ if (sel < 512)
+ continue;
+
+ bank = alu->src[i].kc_bank;
+ line = (sel-512)>>4;
+
+ if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line)))
+ return r;
}
+ return 0;
+}
- /* Filter lines pulled in by previous intructions. Note that this is
- * only for the required_lines count, we can't remove these from the
- * cache_line array since we may have to start a new ALU clause. */
- for (i = 0, required_lines = count; i < count; ++i) {
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
- kcache[j].addr == cache_line[i]) {
- --required_lines;
- break;
+static int r600_bytecode_assign_kcache_banks(struct r600_bytecode *bc,
+ struct r600_bytecode_alu *alu,
+ struct r600_bytecode_kcache * kcache)
+{
+ int i, j;
+
+ /* Alter the src operands to refer to the kcache. */
+ for (i = 0; i < 3; ++i) {
+ static const unsigned int base[] = {128, 160, 256, 288};
+ unsigned int line, sel = alu->src[i].sel, found = 0;
+
+ if (sel < 512)
+ continue;
+
+ sel -= 512;
+ line = sel>>4;
+
+ for (j = 0; j < 4 && !found; ++j) {
+ switch (kcache[j].mode) {
+ case V_SQ_CF_KCACHE_NOP:
+ case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
+ R600_ERR("unexpected kcache line mode\n");
+ return -ENOMEM;
+ default:
+ if (kcache[j].bank == alu->src[i].kc_bank &&
+ kcache[j].addr <= line &&
+ line < kcache[j].addr + kcache[j].mode) {
+ alu->src[i].sel = sel - (kcache[j].addr<<4);
+ alu->src[i].sel += base[j];
+ found=1;
+ }
}
}
}
+ return 0;
+}
+
+static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, int type)
+{
+ struct r600_bytecode_kcache kcache_sets[4];
+ struct r600_bytecode_kcache *kcache = kcache_sets;
+ int r;
- /* Start a new ALU clause if needed. */
- if (required_lines > free_lines) {
+ memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
+
+ if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
+ /* can't alloc, need to start new clause */
if ((r = r600_bytecode_add_cf(bc))) {
return r;
}
bc->cf_last->inst = type;
+
+ /* retry with the new clause */
kcache = bc->cf_last->kcache;
+ if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
+ /* can't alloc again- should never happen */
+ return r;
+ }
+ } else {
+ /* update kcache sets */
+ memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
}
- /* Setup the kcache lines. */
- for (i = 0; i < count; ++i) {
- boolean found = false;
+ /* if we actually used more than 2 kcache sets - use ALU_EXTENDED on eg+ */
+ if (kcache[2].mode != V_SQ_CF_KCACHE_NOP) {
+ if (bc->chip_class < EVERGREEN)
+ return -ENOMEM;
+ bc->cf_last->eg_alu_extended = 1;
+ }
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
- kcache[j].addr == cache_line[i]) {
- found = true;
- break;
- }
- }
+ return 0;
+}
- if (found) continue;
+static int insert_nop_r6xx(struct r600_bytecode *bc)
+{
+ struct r600_bytecode_alu alu;
+ int r, i;
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_NOP) {
- kcache[j].bank = 0;
- kcache[j].addr = cache_line[i];
- kcache[j].mode = V_SQ_CF_KCACHE_LOCK_2;
- break;
- }
- }
+ for (i = 0; i < 4; i++) {
+ memset(&alu, 0, sizeof(alu));
+ alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
+ alu.src[0].chan = i;
+ alu.dst.chan = i;
+ alu.last = (i == 3);
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
}
+ return 0;
+}
- /* Alter the src operands to refer to the kcache. */
- for (i = 0; i < 3; ++i) {
- static const unsigned int base[] = {128, 160, 256, 288};
- unsigned int line;
+/* load AR register from gpr (bc->ar_reg) with MOVA_INT */
+static int load_ar_r6xx(struct r600_bytecode *bc)
+{
+ struct r600_bytecode_alu alu;
+ int r;
- if (alu->src[i].sel < 512)
- continue;
+ if (bc->ar_loaded)
+ return 0;
- alu->src[i].sel -= 512;
- line = (alu->src[i].sel / 32) * 2;
+ /* hack to avoid making MOVA the last instruction in the clause */
+ if ((bc->cf_last->ndw>>1) >= 110)
+ bc->force_add_cf = 1;
- for (j = 0; j < 2; ++j) {
- if (kcache[j].mode == V_SQ_CF_KCACHE_LOCK_2 &&
- kcache[j].addr == line) {
- alu->src[i].sel &= 0x1f;
- alu->src[i].sel += base[j];
- break;
- }
- }
- }
+ memset(&alu, 0, sizeof(alu));
+ alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_GPR_INT;
+ alu.src[0].sel = bc->ar_reg;
+ alu.last = 1;
+ alu.index_mode = INDEX_MODE_LOOP;
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
+ /* no requirement to set uses waterfall on MOVA_GPR_INT */
+ bc->ar_loaded = 1;
return 0;
}
struct r600_bytecode_alu alu;
int r;
+ if (bc->ar_handling)
+ return load_ar_r6xx(bc);
+
if (bc->ar_loaded)
return 0;
bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
bc->cf_last->curr_bs_head = NULL;
}
+
+ if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
+ insert_nop_r6xx(bc);
+
return 0;
}
bc->ndw += 4;
if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
bc->force_add_cf = 1;
+
+ bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
+ bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
+
return 0;
}
S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
+ S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
S_SQ_ALU_WORD0_LAST(alu->last);
if (alu->is_op3) {
case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
+ case CF_NATIVE:
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
if (r)
return r;
r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
+ r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
+
switch(bc->chip_class) {
case EVERGREEN: /* eg alu is same encoding as r700 */
case CAYMAN:
}
break;
case EG_V_SQ_CF_WORD1_SQ_CF_INST_TEX:
- if (bc->chip_class == CAYMAN) {
- LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
- r = r600_bytecode_vtx_build(bc, vtx, addr);
- if (r)
- return r;
- addr += 4;
- }
+ LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
+ assert(bc->chip_class >= EVERGREEN);
+ r = r600_bytecode_vtx_build(bc, vtx, addr);
+ if (r)
+ return r;
+ addr += 4;
}
LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
r = r600_bytecode_tex_build(bc, tex, addr);
case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
break;
+ case CF_NATIVE:
+ break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
if (r)
return r;
r600_bytecode_alu_adjust_literals(bc, alu, literal, nliteral);
+ r600_bytecode_assign_kcache_banks(bc, alu, cf->kcache);
+
switch(bc->chip_class) {
case R600:
r = r600_bytecode_alu_build(bc, alu, addr);
case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER:
case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER:
case EG_V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE:
+ if (cf->eg_alu_extended) {
+ fprintf(stderr, "%04d %08X ALU_EXT0 ", id, bc->bytecode[id]);
+ fprintf(stderr, "KCACHE_BANK2:%X ", cf->kcache[2].bank);
+ fprintf(stderr, "KCACHE_BANK3:%X ", cf->kcache[3].bank);
+ fprintf(stderr, "KCACHE_MODE2:%X\n", cf->kcache[2].mode);
+ id++;
+ fprintf(stderr, "%04d %08X ALU_EXT1 ", id, bc->bytecode[id]);
+ fprintf(stderr, "KCACHE_MODE3:%X ", cf->kcache[3].mode);
+ fprintf(stderr, "KCACHE_ADDR2:%X ", cf->kcache[2].addr);
+ fprintf(stderr, "KCACHE_ADDR3:%X\n", cf->kcache[3].addr);
+ id++;
+ }
+
fprintf(stderr, "%04d %08X ALU ", id, bc->bytecode[id]);
fprintf(stderr, "ADDR:%d ", cf->addr);
fprintf(stderr, "KCACHE_MODE0:%X ", cf->kcache[0].mode);
fprintf(stderr, "COND:%X ", cf->cond);
fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
break;
+ case CF_NATIVE:
+ fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
+ fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
+ break;
default:
R600_ERR("Unknown instruction %0x\n", cf->inst);
}
fprintf(stderr, "SRC1(SEL:%d ", alu->src[1].sel);
fprintf(stderr, "REL:%d ", alu->src[1].rel);
fprintf(stderr, "CHAN:%d ", alu->src[1].chan);
- fprintf(stderr, "NEG:%d) ", alu->src[1].neg);
+ fprintf(stderr, "NEG:%d ", alu->src[1].neg);
+ fprintf(stderr, "IM:%d) ", alu->index_mode);
fprintf(stderr, "LAST:%d)\n", alu->last);
id++;
fprintf(stderr, "%04d %08X %c ", id, bc->bytecode[id], alu->last ? '*' : ' ');
if (alu->last) {
for (i = 0; i < nliteral; i++, id++) {
float *f = (float*)(bc->bytecode + id);
- fprintf(stderr, "%04d %08X\t%f\n", id, bc->bytecode[id], *f);
+ fprintf(stderr, "%04d %08X\t%f (%d)\n", id, bc->bytecode[id], *f,
+ *(bc->bytecode + id));
}
id += nliteral & 1;
nliteral = 0;
fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
fprintf(stderr, "ENDIAN:%d ", vtx->endian);
fprintf(stderr, "OFFSET:%d\n", vtx->offset);
- /* TODO */
+ /* XXX */
id++;
fprintf(stderr, "%04d %08X \n", id, bc->bytecode[id]);
id++;
R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
}
-int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, struct r600_vertex_element *ve)
+int r600_vertex_elements_build_fetch_shader(struct r600_context *rctx, struct r600_vertex_element *ve)
{
static int dump_shaders = -1;
const struct util_format_description *desc;
unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
unsigned format, num_format, format_comp, endian;
- u32 *bytecode;
+ uint32_t *bytecode;
int i, r;
- /* Vertex element offsets need special handling. If the offset is
- * bigger than what we can put in the fetch instruction we need to
- * alter the vertex resource offset. In order to simplify code we
- * will bind one resource per element in such cases. It's a worst
- * case scenario. */
- for (i = 0; i < ve->count; i++) {
- ve->vbuffer_offset[i] = C_SQ_VTX_WORD2_OFFSET & elements[i].src_offset;
- if (ve->vbuffer_offset[i]) {
- ve->vbuffer_need_offset = 1;
- }
- }
-
memset(&bc, 0, sizeof(bc));
- r600_bytecode_init(&bc, rctx->chip_class);
+ r600_bytecode_init(&bc, rctx->chip_class, rctx->family);
for (i = 0; i < ve->count; i++) {
if (elements[i].instance_divisor > 1) {
}
for (i = 0; i < ve->count; i++) {
- unsigned vbuffer_index;
r600_vertex_data_type(ve->elements[i].src_format,
&format, &num_format, &format_comp, &endian);
+
desc = util_format_description(ve->elements[i].src_format);
if (desc == NULL) {
r600_bytecode_clear(&bc);
return -EINVAL;
}
- /* see above for vbuffer_need_offset explanation */
- vbuffer_index = elements[i].vertex_buffer_index;
+ if (elements[i].src_offset > 65535) {
+ r600_bytecode_clear(&bc);
+ R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
+ return -EINVAL;
+ }
+
memset(&vtx, 0, sizeof(vtx));
- vtx.buffer_id = (ve->vbuffer_need_offset ? i : vbuffer_index) + fetch_resource_start;
+ vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
vtx.fetch_type = elements[i].instance_divisor ? 1 : 0;
vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
return -ENOMEM;
}
- bytecode = rctx->ws->buffer_map(ve->fetch_shader->buf, rctx->ctx.cs, PIPE_TRANSFER_WRITE);
+ bytecode = rctx->ws->buffer_map(ve->fetch_shader->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
if (bytecode == NULL) {
r600_bytecode_clear(&bc);
pipe_resource_reference((struct pipe_resource**)&ve->fetch_shader, NULL);
memcpy(bytecode, bc.bytecode, ve->fs_size);
}
- rctx->ws->buffer_unmap(ve->fetch_shader->buf);
+ rctx->ws->buffer_unmap(ve->fetch_shader->cs_buf);
r600_bytecode_clear(&bc);
if (rctx->chip_class >= EVERGREEN)
projects / mesa.git / blobdiff