r600g/sb: fix issues cause by GLSL switching to loops for switch

[mesa.git] / src / gallium / drivers / r600 / r600_asm.h

diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index c1aa3bae4e3aa4598127f8de923029b0e78f23c9..e37d92672bd0ceef59125586905a4b1638bb30c4 100644 (file)
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -33,6 +33,7 @@ struct r600_bytecode_alu_src {
        unsigned                        abs;
        unsigned                        rel;
        unsigned                        kc_bank;
+       unsigned                        kc_rel;
        uint32_t                        value;
 };
 
@@ -86,6 +87,9 @@ struct r600_bytecode_tex {
        unsigned                        src_sel_y;
        unsigned                        src_sel_z;
        unsigned                        src_sel_w;
+       /* indexed samplers/resources only on evergreen/cayman */
+       unsigned                        sampler_index_mode;
+       unsigned                        resource_index_mode;
 };
 
 struct r600_bytecode_vtx {
@@ -108,6 +112,7 @@ struct r600_bytecode_vtx {
        unsigned                        srf_mode_all;
        unsigned                        offset;
        unsigned                        endian;
+       unsigned                        buffer_index_mode;
 };
 
 struct r600_bytecode_output {
@@ -115,7 +120,6 @@ struct r600_bytecode_output {
        unsigned                        array_size;
        unsigned                        comp_mask;
        unsigned                        type;
-       unsigned                        end_of_program;
 
        unsigned                        op;
 
@@ -126,13 +130,14 @@ struct r600_bytecode_output {
        unsigned                        swizzle_z;
        unsigned                        swizzle_w;
        unsigned                        burst_count;
-       unsigned                        barrier;
+       unsigned                        index_gpr;
 };
 
 struct r600_bytecode_kcache {
        unsigned                        bank;
        unsigned                        mode;
        unsigned                        addr;
+       unsigned                        index_mode;
 };
 
 struct r600_bytecode_cf {
@@ -148,6 +153,8 @@ struct r600_bytecode_cf {
        struct r600_bytecode_kcache             kcache[4];
        unsigned                        r6xx_uses_waterfall;
        unsigned                        eg_alu_extended;
+       unsigned                        barrier;
+       unsigned                        end_of_program;
        struct list_head                alu;
        struct list_head                tex;
        struct list_head                vtx;
@@ -173,20 +180,30 @@ struct r600_cf_stack_entry {
 };
 
 #define SQ_MAX_CALL_DEPTH 0x00000020
-struct r600_cf_callstack {
-       unsigned                        fc_sp_before_entry;
-       int                             sub_desc_index;
-       int                             current;
-       int                             max;
-};
 
 #define AR_HANDLE_NORMAL 0
 #define AR_HANDLE_RV6XX 1 /* except RV670 */
 
+struct r600_stack_info {
+       /* current level of non-WQM PUSH operations
+        * (PUSH, PUSH_ELSE, ALU_PUSH_BEFORE) */
+       int push;
+       /* current level of WQM PUSH operations
+        * (PUSH, PUSH_ELSE, PUSH_WQM) */
+       int push_wqm;
+       /* current loop level */
+       int loop;
+
+       /* required depth */
+       int max_entries;
+       /* subentries per entry */
+       int entry_size;
+};
 
 struct r600_bytecode {
        enum chip_class                 chip_class;
-       enum r600_msaa_texture_mode     msaa_texture_mode;
+       enum radeon_family              family;
+       bool                            has_compressed_msaa_texturing;
        int                             type;
        struct list_head                cf;
        struct r600_bytecode_cf         *cf_last;
@@ -194,29 +211,33 @@ struct r600_bytecode {
        unsigned                        ncf;
        unsigned                        ngpr;
        unsigned                        nstack;
+       unsigned                        nlds_dw;
        unsigned                        nresource;
        unsigned                        force_add_cf;
        uint32_t                        *bytecode;
        uint32_t                        fc_sp;
        struct r600_cf_stack_entry      fc_stack[32];
-       unsigned                        call_sp;
-       struct r600_cf_callstack        callstack[SQ_MAX_CALL_DEPTH];
+       struct r600_stack_info          stack;
        unsigned        ar_loaded;
        unsigned        ar_reg;
        unsigned        ar_chan;
        unsigned        ar_handling;
        unsigned        r6xx_nop_after_rel_dst;
+       bool            index_loaded[2];
+       unsigned        index_reg[2]; /* indexing register CF_INDEX_[01] */
+       unsigned        debug_id;
        struct r600_isa* isa;
 };
 
 /* eg_asm.c */
 int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf);
+int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_clause);
 
 /* r600_asm.c */
 void r600_bytecode_init(struct r600_bytecode *bc,
                        enum chip_class chip_class,
                        enum radeon_family family,
-                       enum r600_msaa_texture_mode msaa_texture_mode);
+                       bool has_compressed_msaa_texturing);
 void r600_bytecode_clear(struct r600_bytecode *bc);
 int r600_bytecode_add_alu(struct r600_bytecode *bc,
                const struct r600_bytecode_alu *alu);