lima/ppir: enable vectorize optimization

[mesa.git] / src / gallium / drivers / r600 / r600_buffer_common.c

diff --git a/src/gallium/drivers/r600/r600_buffer_common.c b/src/gallium/drivers/r600/r600_buffer_common.c
index 501b96fa0baef1cfa9c95448591863779e1ac13c..04f80daec1d6ab86b7df8a61e63496ab786f89b1 100644 (file)
--- a/src/gallium/drivers/r600/r600_buffer_common.c
+++ b/src/gallium/drivers/r600/r600_buffer_common.c
@@ -126,8 +126,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
                /* Older kernels didn't always flush the HDP cache before
                 * CS execution
                 */
-               if (rscreen->info.drm_major == 2 &&
-                   rscreen->info.drm_minor < 40) {
+               if (rscreen->info.drm_minor < 40) {
                        res->domains = RADEON_DOMAIN_GTT;
                        res->flags |= RADEON_FLAG_GTT_WC;
                        break;
@@ -154,8 +153,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
                 * ensures all CPU writes finish before the GPU
                 * executes a command stream.
                 */
-               if (rscreen->info.drm_major == 2 &&
-                   rscreen->info.drm_minor < 40)
+               if (rscreen->info.drm_minor < 40)
                        res->domains = RADEON_DOMAIN_GTT;
        }
 
@@ -167,21 +165,15 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
                         RADEON_FLAG_GTT_WC;
        }
 
-       /* Only displayable single-sample textures can be shared between
-        * processes. */
-       if (res->b.b.target == PIPE_BUFFER ||
-           res->b.b.nr_samples >= 2 ||
-           (rtex->surface.micro_tile_mode != RADEON_MICRO_MODE_DISPLAY &&
-            /* Raven doesn't use display micro mode for 32bpp, so check this: */
-            !(res->b.b.bind & PIPE_BIND_SCANOUT)))
+       /* Displayable and shareable surfaces are not suballocated. */
+       if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
+               res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
+       else
                res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
 
        if (rscreen->debug_flags & DBG_NO_WC)
                res->flags &= ~RADEON_FLAG_GTT_WC;
 
-       if (res->b.b.bind & PIPE_BIND_SHARED)
-               res->flags |= RADEON_FLAG_NO_SUBALLOC;
-
        /* Set expected VRAM and GART usage for the buffer. */
        res->vram_usage = 0;
        res->gart_usage = 0;
@@ -212,7 +204,7 @@ bool r600_alloc_resource(struct r600_common_screen *rscreen,
        old_buf = res->buf;
        res->buf = new_buf; /* should be atomic */
 
-       if (rscreen->info.has_virtual_memory)
+       if (rscreen->info.r600_has_virtual_memory)
                res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
        else
                res->gpu_address = 0;
@@ -553,12 +545,13 @@ void r600_buffer_subdata(struct pipe_context *ctx,
        struct pipe_box box;
        uint8_t *map = NULL;
 
+       usage |= PIPE_TRANSFER_WRITE;
+
+       if (!(usage & PIPE_TRANSFER_MAP_DIRECTLY))
+               usage |= PIPE_TRANSFER_DISCARD_RANGE;
+
        u_box_1d(offset, size, &box);
-       map = r600_buffer_transfer_map(ctx, buffer, 0,
-                                      PIPE_TRANSFER_WRITE |
-                                      PIPE_TRANSFER_DISCARD_RANGE |
-                                      usage,
-                                      &box, &transfer);
+       map = r600_buffer_transfer_map(ctx, buffer, 0, usage, &box, &transfer);
        if (!map)
                return;
 
@@ -660,7 +653,7 @@ r600_buffer_from_user_memory(struct pipe_screen *screen,
                return NULL;
        }
 
-       if (rscreen->info.has_virtual_memory)
+       if (rscreen->info.r600_has_virtual_memory)
                rbuffer->gpu_address =
                        ws->buffer_get_virtual_address(rbuffer->buf);
        else