/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
- if (rscreen->info.drm_major == 2 &&
- rscreen->info.drm_minor < 40) {
+ if (rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
res->flags |= RADEON_FLAG_GTT_WC;
break;
* ensures all CPU writes finish before the GPU
* executes a command stream.
*/
- if (rscreen->info.drm_major == 2 &&
- rscreen->info.drm_minor < 40)
+ if (rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
}
old_buf = res->buf;
res->buf = new_buf; /* should be atomic */
- if (rscreen->info.has_virtual_memory)
+ if (rscreen->info.r600_has_virtual_memory)
res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf);
else
res->gpu_address = 0;
struct pipe_box box;
uint8_t *map = NULL;
+ usage |= PIPE_TRANSFER_WRITE;
+
+ if (!(usage & PIPE_TRANSFER_MAP_DIRECTLY))
+ usage |= PIPE_TRANSFER_DISCARD_RANGE;
+
u_box_1d(offset, size, &box);
- map = r600_buffer_transfer_map(ctx, buffer, 0,
- PIPE_TRANSFER_WRITE |
- PIPE_TRANSFER_DISCARD_RANGE |
- usage,
- &box, &transfer);
+ map = r600_buffer_transfer_map(ctx, buffer, 0, usage, &box, &transfer);
if (!map)
return;
return NULL;
}
- if (rscreen->info.has_virtual_memory)
+ if (rscreen->info.r600_has_virtual_memory)
rbuffer->gpu_address =
ws->buffer_get_virtual_address(rbuffer->buf);
else