#ifndef R600_FORMATS_H
#define R600_FORMATS_H
+#include "util/u_format.h"
+#include "r600_pipe.h"
+
/* list of formats from R700 ISA document - apply across GPUs in different registers */
#define FMT_INVALID 0x00000000
#define FMT_8 0x00000001
#define FMT_BC3 0x00000033
#define FMT_BC4 0x00000034
#define FMT_BC5 0x00000035
+#define FMT_BC6 0x00000036
+#define FMT_BC7 0x00000037
+#define FMT_32_AS_32_32_32_32 0x00000038
+
+#define ENDIAN_NONE 0
+#define ENDIAN_8IN16 1
+#define ENDIAN_8IN32 2
+#define ENDIAN_8IN64 3
+
+static INLINE unsigned r600_endian_swap(unsigned size)
+{
+ if (R600_BIG_ENDIAN) {
+ switch (size) {
+ case 64:
+ return ENDIAN_8IN64;
+ case 32:
+ return ENDIAN_8IN32;
+ case 16:
+ return ENDIAN_8IN16;
+ default:
+ return ENDIAN_NONE;
+ }
+ } else {
+ return ENDIAN_NONE;
+ }
+}
+
+static INLINE bool r600_is_vertex_format_supported(enum pipe_format format)
+{
+ const struct util_format_description *desc = util_format_description(format);
+ unsigned i;
+
+ if (format == PIPE_FORMAT_R11G11B10_FLOAT)
+ return true;
+
+ if (!desc)
+ return false;
+
+ /* Find the first non-VOID channel. */
+ for (i = 0; i < 4; i++) {
+ if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID)
+ break;
+ }
+ if (i == 4)
+ return false;
+
+ /* No fixed, no double. */
+ if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
+ (desc->channel[i].size == 64 &&
+ desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) ||
+ desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
+ return false;
+
+ /* No scaled/norm formats with 32 bits per channel. */
+ if (desc->channel[i].size == 32 &&
+ !desc->channel[i].pure_integer &&
+ (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED ||
+ desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED))
+ return false;
+
+ return true;
+}
#endif