block->pm4[block->pm4_ndwords++] = 0x00000000;
block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1;
}
- if ((ctx->family > CHIP_R600) &&
- (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) {
- block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0);
- block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags;
- }
}
/* check that we stay in limit */
assert(block->pm4_ndwords < R600_BLOCK_MAX_REG);
/* R600/R700 configuration */
static const struct r600_reg r600_config_reg_list[] = {
- {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
- {R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, 0, 0},
- {R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, 0, 0},
- {R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 0, 0},
- {R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, 0, 0},
{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
};
-static const struct r600_reg r600_ctl_const_list[] = {
- {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
static const struct r600_reg r600_context_reg_list[] = {
{R_028A4C_PA_SC_MODE_CNTL, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0},
- {R_028060_CB_COLOR0_SIZE, 0, 0},
- {R_028080_CB_COLOR0_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028100_CB_COLOR0_MASK, 0, 0},
- {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
- {R_028064_CB_COLOR1_SIZE, 0, 0},
- {R_028084_CB_COLOR1_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
- {R_028104_CB_COLOR1_MASK, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0},
- {R_028068_CB_COLOR2_SIZE, 0, 0},
- {R_028088_CB_COLOR2_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
- {R_028108_CB_COLOR2_MASK, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0},
- {R_02806C_CB_COLOR3_SIZE, 0, 0},
- {R_02808C_CB_COLOR3_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
- {R_02810C_CB_COLOR3_MASK, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0},
- {R_028070_CB_COLOR4_SIZE, 0, 0},
- {R_028090_CB_COLOR4_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
- {R_028110_CB_COLOR4_MASK, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0},
- {R_028074_CB_COLOR5_SIZE, 0, 0},
- {R_028094_CB_COLOR5_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
- {R_028114_CB_COLOR5_MASK, 0, 0},
- {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
- {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
- {R_028078_CB_COLOR6_SIZE, 0, 0},
- {R_028098_CB_COLOR6_VIEW, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
- {R_028118_CB_COLOR6_MASK, 0, 0},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
- {GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0},
- {R_02807C_CB_COLOR7_SIZE, 0, 0},
- {R_02809C_CB_COLOR7_VIEW, 0, 0},
- {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
- {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
- {R_02811C_CB_COLOR7_MASK, 0, 0},
- {R_028120_CB_CLEAR_RED, 0, 0},
- {R_028124_CB_CLEAR_GREEN, 0, 0},
- {R_028128_CB_CLEAR_BLUE, 0, 0},
- {R_02812C_CB_CLEAR_ALPHA, 0, 0},
- {R_028414_CB_BLEND_RED, 0, 0},
- {R_028418_CB_BLEND_GREEN, 0, 0},
- {R_02841C_CB_BLEND_BLUE, 0, 0},
- {R_028420_CB_BLEND_ALPHA, 0, 0},
- {R_028424_CB_FOG_RED, 0, 0},
- {R_028428_CB_FOG_GREEN, 0, 0},
- {R_02842C_CB_FOG_BLUE, 0, 0},
{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0},
{R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0},
- {R_0287A0_CB_SHADER_CONTROL, 0, 0},
{R_028800_DB_DEPTH_CONTROL, 0, 0},
{R_028804_CB_BLEND_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
- {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
- {R_028000_DB_DEPTH_SIZE, 0, 0},
- {R_028004_DB_DEPTH_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
- {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
- {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
- {R_028D34_DB_PREFETCH_LIMIT, 0, 0},
{R_028D44_DB_ALPHA_TO_MASK, 0, 0},
- {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
- {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
- {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
- {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
- {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
- {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
- {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
- {R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
- {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
- {R_028C00_PA_SC_LINE_CNTL, 0, 0},
- {R_028C04_PA_SC_AA_CONFIG, 0, 0},
{R_028C08_PA_SU_VTX_CNTL, 0, 0},
{R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
{R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
{R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
{R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
- {R_028E20_PA_CL_UCP0_X, 0, 0},
- {R_028E24_PA_CL_UCP0_Y, 0, 0},
- {R_028E28_PA_CL_UCP0_Z, 0, 0},
- {R_028E2C_PA_CL_UCP0_W, 0, 0},
- {R_028E30_PA_CL_UCP1_X, 0, 0},
- {R_028E34_PA_CL_UCP1_Y, 0, 0},
- {R_028E38_PA_CL_UCP1_Z, 0, 0},
- {R_028E3C_PA_CL_UCP1_W, 0, 0},
- {R_028E40_PA_CL_UCP2_X, 0, 0},
- {R_028E44_PA_CL_UCP2_Y, 0, 0},
- {R_028E48_PA_CL_UCP2_Z, 0, 0},
- {R_028E4C_PA_CL_UCP2_W, 0, 0},
- {R_028E50_PA_CL_UCP3_X, 0, 0},
- {R_028E54_PA_CL_UCP3_Y, 0, 0},
- {R_028E58_PA_CL_UCP3_Z, 0, 0},
- {R_028E5C_PA_CL_UCP3_W, 0, 0},
- {R_028E60_PA_CL_UCP4_X, 0, 0},
- {R_028E64_PA_CL_UCP4_Y, 0, 0},
- {R_028E68_PA_CL_UCP4_Z, 0, 0},
- {R_028E6C_PA_CL_UCP4_W, 0, 0},
- {R_028E70_PA_CL_UCP5_X, 0, 0},
- {R_028E74_PA_CL_UCP5_Y, 0, 0},
- {R_028E78_PA_CL_UCP5_Z, 0, 0},
- {R_028E7C_PA_CL_UCP5_W, 0, 0},
{R_028350_SX_MISC, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
{R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
- {R_028408_VGT_INDX_OFFSET, 0, 0},
- {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
- {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
- {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
- {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
};
-static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
-{
- unsigned nreg = 32;
- struct r600_reg r600_loop_consts[32];
- int i;
-
- for (i = 0; i < nreg; i++) {
- r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
- r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
- r600_loop_consts[i].sbu_flags = 0;
- }
- return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
-}
-
/* initialize */
void r600_context_fini(struct r600_context *ctx)
{
Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
if (r)
goto out_err;
- r = r600_context_add_block(ctx, r600_ctl_const_list,
- Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
- if (r)
- goto out_err;
-
- /* PS loop const */
- r600_loop_const_init(ctx, 0);
- /* VS loop const */
- r600_loop_const_init(ctx, 32);
r = r600_setup_block_table(ctx);
if (r)
num_dw += ctx->pm4_dirty_cdwords;
- /* The upper-bound of how much a draw command would take. */
- num_dw += R600_MAX_DRAW_CS_DWORDS;
+ /* The upper-bound of how much space a draw command would take. */
+ num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
}
/* Count in queries_suspend. */
num_dw += 3;
}
+ /* SX_MISC */
+ if (ctx->chip_class <= R700) {
+ num_dw += 3;
+ }
+
/* Count in framebuffer cache flushes at the end of CS. */
- num_dw += 44; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
+ num_dw += R600_MAX_FLUSH_CS_DWORDS;
- /* Save 16 dwords for the fence mechanism. */
- num_dw += 16;
+ /* The fence at the end of CS. */
+ num_dw += 10;
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
}
+ if (rctx->chip_class >= R700 &&
+ (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB_META)) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+ cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0);
+ }
+
if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
}
/* force to keep tiling flags */
- flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ if (ctx->keep_tiling_flags) {
+ flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+ }
/* Flush the CS. */
ctx->ws->cs_flush(ctx->cs, flags);
/* Re-emit states. */
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
+ r600_atom_dirty(ctx, &ctx->blend_color.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->framebuffer.atom);
+ r600_atom_dirty(ctx, &ctx->vgt_state.atom);
+ r600_atom_dirty(ctx, &ctx->vgt2_state.atom);
r600_atom_dirty(ctx, &ctx->sample_mask.atom);
r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
+ r600_atom_dirty(ctx, &ctx->viewport.atom);
if (ctx->chip_class <= R700) {
r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
enable_block->nreg_dirty = enable_block->nreg;
}
+
+ /* Re-emit the draw state. */
+ ctx->last_primitive_type = -1;
+ ctx->last_start_instance = -1;
}
void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
{
struct radeon_winsys_cs *cs = ctx->cs;
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = 0;
+ r600_write_config_reg(cs, R_008490_CP_STRMOUT_CNTL, 0);
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0);
struct radeon_winsys_cs *cs = ctx->cs;
if (buffer_enable_bit) {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1);
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = buffer_enable_bit;
+ r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(1));
+ r600_write_context_reg(cs, R_028B20_VGT_STRMOUT_BUFFER_EN, buffer_enable_bit);
} else {
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0);
+ r600_write_context_reg(cs, R_028AB0_VGT_STRMOUT_EN, S_028AB0_STREAMOUT(0));
}
}
update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0);
- cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
- 16*i - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = (t[i]->b.buffer_offset +
- t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */
- cs->buf[cs->cdw++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */
- cs->buf[cs->cdw++] = va >> 8; /* BUFFER_BASE */
+ r600_write_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
+ r600_write_value(cs, (t[i]->b.buffer_offset +
+ t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
+ r600_write_value(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
+ r600_write_value(cs, va >> 8); /* BUFFER_BASE */
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] =
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