{R_028124_CB_CLEAR_GREEN, 0, 0},
{R_028128_CB_CLEAR_BLUE, 0, 0},
{R_02812C_CB_CLEAR_ALPHA, 0, 0},
- {R_028414_CB_BLEND_RED, 0, 0},
- {R_028418_CB_BLEND_GREEN, 0, 0},
- {R_02841C_CB_BLEND_BLUE, 0, 0},
- {R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028424_CB_FOG_RED, 0, 0},
{R_028428_CB_FOG_GREEN, 0, 0},
{R_02842C_CB_FOG_BLUE, 0, 0},
- {R_028430_DB_STENCILREFMASK, 0, 0},
- {R_028434_DB_STENCILREFMASK_BF, 0, 0},
{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
- {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
- {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
- {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
- {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
- {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
{R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
{R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
{R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
- {R_028E20_PA_CL_UCP0_X, 0, 0},
- {R_028E24_PA_CL_UCP0_Y, 0, 0},
- {R_028E28_PA_CL_UCP0_Z, 0, 0},
- {R_028E2C_PA_CL_UCP0_W, 0, 0},
- {R_028E30_PA_CL_UCP1_X, 0, 0},
- {R_028E34_PA_CL_UCP1_Y, 0, 0},
- {R_028E38_PA_CL_UCP1_Z, 0, 0},
- {R_028E3C_PA_CL_UCP1_W, 0, 0},
- {R_028E40_PA_CL_UCP2_X, 0, 0},
- {R_028E44_PA_CL_UCP2_Y, 0, 0},
- {R_028E48_PA_CL_UCP2_Z, 0, 0},
- {R_028E4C_PA_CL_UCP2_W, 0, 0},
- {R_028E50_PA_CL_UCP3_X, 0, 0},
- {R_028E54_PA_CL_UCP3_Y, 0, 0},
- {R_028E58_PA_CL_UCP3_Z, 0, 0},
- {R_028E5C_PA_CL_UCP3_W, 0, 0},
- {R_028E60_PA_CL_UCP4_X, 0, 0},
- {R_028E64_PA_CL_UCP4_Y, 0, 0},
- {R_028E68_PA_CL_UCP4_Z, 0, 0},
- {R_028E6C_PA_CL_UCP4_W, 0, 0},
- {R_028E70_PA_CL_UCP5_X, 0, 0},
- {R_028E74_PA_CL_UCP5_Y, 0, 0},
- {R_028E78_PA_CL_UCP5_Z, 0, 0},
- {R_028E7C_PA_CL_UCP5_W, 0, 0},
{R_028350_SX_MISC, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
unsigned i;
/* The number of dwords all the dirty states would take. */
- for (i = 0; i < R600_MAX_ATOM; i++) {
+ for (i = 0; i < R600_NUM_ATOMS; i++) {
if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
num_dw += ctx->atoms[i]->num_dw;
}
void r600_context_flush(struct r600_context *ctx, unsigned flags)
{
struct radeon_winsys_cs *cs = ctx->cs;
- struct r600_block *enable_block = NULL;
- bool timer_queries_suspended = false;
- bool nontimer_queries_suspended = false;
- bool streamout_suspended = false;
if (cs->cdw == ctx->start_cs_cmd.atom.num_dw)
return;
+ ctx->timer_queries_suspended = false;
+ ctx->nontimer_queries_suspended = false;
+ ctx->streamout_suspended = false;
+
/* suspend queries */
if (ctx->num_cs_dw_timer_queries_suspend) {
r600_suspend_timer_queries(ctx);
- timer_queries_suspended = true;
+ ctx->timer_queries_suspended = true;
}
if (ctx->num_cs_dw_nontimer_queries_suspend) {
r600_suspend_nontimer_queries(ctx);
- nontimer_queries_suspended = true;
+ ctx->nontimer_queries_suspended = true;
}
if (ctx->num_cs_dw_streamout_end) {
r600_context_streamout_end(ctx);
- streamout_suspended = true;
+ ctx->streamout_suspended = true;
}
/* partial flush is needed to avoid lockups on some chips with user fences */
/* Flush the CS. */
ctx->ws->cs_flush(ctx->cs, flags);
+ r600_begin_new_cs(ctx);
+}
+
+void r600_begin_new_cs(struct r600_context *ctx)
+{
+ struct r600_block *enable_block = NULL;
+ unsigned shader;
+
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
/* Re-emit states. */
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
+ r600_atom_dirty(ctx, &ctx->blend_color.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
- /* reemit sampler, will only matter if atom_sampler.num_dw != 0 */
- r600_atom_dirty(ctx, &ctx->vs_samplers.atom_sampler);
- r600_atom_dirty(ctx, &ctx->ps_samplers.atom_sampler);
+ r600_atom_dirty(ctx, &ctx->sample_mask.atom);
+ r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
+ r600_atom_dirty(ctx, &ctx->viewport.atom);
+
if (ctx->chip_class <= R700) {
r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
}
- r600_atom_dirty(ctx, &ctx->sample_mask.atom);
ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
r600_vertex_buffers_dirty(ctx);
- ctx->vs_constbuf_state.dirty_mask = ctx->vs_constbuf_state.enabled_mask;
- ctx->ps_constbuf_state.dirty_mask = ctx->ps_constbuf_state.enabled_mask;
- r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state);
- r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state);
+ /* Re-emit shader resources. */
+ for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
+ struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
+ struct r600_textures_info *samplers = &ctx->samplers[shader];
+
+ constbuf->dirty_mask = constbuf->enabled_mask;
+ samplers->views.dirty_mask = samplers->views.enabled_mask;
+ samplers->states.dirty_mask = samplers->states.enabled_mask;
- ctx->vs_samplers.views.dirty_mask = ctx->vs_samplers.views.enabled_mask;
- ctx->ps_samplers.views.dirty_mask = ctx->ps_samplers.views.enabled_mask;
- r600_sampler_views_dirty(ctx, &ctx->vs_samplers.views);
- r600_sampler_views_dirty(ctx, &ctx->ps_samplers.views);
+ r600_constant_buffers_dirty(ctx, constbuf);
+ r600_sampler_views_dirty(ctx, &samplers->views);
+ r600_sampler_states_dirty(ctx, &samplers->states);
+ }
- if (streamout_suspended) {
+ if (ctx->streamout_suspended) {
ctx->streamout_start = TRUE;
ctx->streamout_append_bitmask = ~0;
}
/* resume queries */
- if (timer_queries_suspended) {
+ if (ctx->timer_queries_suspended) {
r600_resume_timer_queries(ctx);
}
- if (nontimer_queries_suspended) {
+ if (ctx->nontimer_queries_suspended) {
r600_resume_nontimer_queries(ctx);
}
projects / mesa.git / blobdiff