static const struct r600_reg r600_config_reg_list[] = {
{R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
- {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
};
static const struct r600_reg r600_ctl_const_list[] = {
{R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
+ {R_028D44_DB_ALPHA_TO_MASK, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
};
-/* SHADER SAMPLER R600/R700/EG/CM */
-int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
-{
- struct r600_reg r600_shader_sampler[] = {
- {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
- {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
- {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler);
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler[i].offset += offset;
- }
- return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
-}
-
-/* SHADER SAMPLER BORDER R600/R700 */
-static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
-{
- struct r600_reg r600_shader_sampler_border[] = {
- {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
- {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
- {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
- {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler_border);
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler_border[i].offset += offset;
- }
- return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
-}
-
static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
if (r)
goto out_err;
- /* PS SAMPLER BORDER */
- for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
- r = r600_state_sampler_border_init(ctx, offset);
- if (r)
- goto out_err;
- }
-
- /* VS SAMPLER BORDER */
- for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
- r = r600_state_sampler_border_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* PS SAMPLER */
- for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER */
- for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
-
/* PS loop const */
r600_loop_const_init(ctx, 0);
/* VS loop const */
}
}
-void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
-{
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(offset)];
- block = range->blocks[CTX_BLOCK_ID(offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
-
- for (i = 0; i < 3; i++) {
- if (block->reg[i] != state->regs[i].value) {
- block->reg[i] = state->regs[i].value;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
- }
-
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 2);
-}
-
-static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
-{
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(offset)];
- block = range->blocks[CTX_BLOCK_ID(offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- if (state->nregs <= 3) {
- return;
- }
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
- for (i = 0; i < 4; i++) {
- if (block->reg[i] != state->regs[i + 3].value) {
- block->reg[i] = state->regs[i + 3].value;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
- }
-
- /* We have to flush the shaders before we change the border color
- * registers, or previous draw commands that haven't completed yet
- * will end up using the new border color. */
- if (dirty & R600_BLOCK_STATUS_DIRTY)
- r600_context_ps_partial_flush(ctx);
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 3);
-}
-
-void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
- r600_context_pipe_state_set_sampler(ctx, state, offset);
- offset = R_00A400_TD_PS_SAMPLER0_BORDER_RED + 16*id;
- r600_context_pipe_state_set_sampler_border(ctx, state, offset);
-}
-
-void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
- r600_context_pipe_state_set_sampler(ctx, state, offset);
- offset = R_00A600_TD_VS_SAMPLER0_BORDER_RED + 16*id;
- r600_context_pipe_state_set_sampler_border(ctx, state, offset);
-}
-
/**
* @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
* block will be used for compute shaders.
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
+ /* reemit sampler, will only matter if atom_sampler.num_dw != 0 */
+ r600_atom_dirty(ctx, &ctx->vs_samplers.atom_sampler);
+ r600_atom_dirty(ctx, &ctx->ps_samplers.atom_sampler);
+ if (ctx->chip_class <= R700) {
+ r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
+ }
+ r600_atom_dirty(ctx, &ctx->sample_mask.atom);
ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
r600_vertex_buffers_dirty(ctx);
r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
ctx->num_cs_dw_streamout_end = 0;
-
-#if 0
- for (i = 0; i < ctx->num_so_targets; i++) {
- if (!t[i])
- continue;
-
- uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ);
- printf("FILLED_SIZE%i: %u\n", i, *ptr);
- ctx->ws->buffer_unmap(t[i]->filled_size->buf);
- }
-#endif
-}
-
-void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
- uint64_t va = r600_resource_va(&ctx->screen->screen,
- (void*)t->filled_size);
-
- r600_need_cs_space(ctx, 14 + 21, TRUE);
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = 0;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = t->stride_in_dw;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
- cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
- cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
- cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
- cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
- cs->buf[cs->cdw++] = 0; /* unused */
-
- cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
}
projects / mesa.git / blobdiff