uint32_t *results;
unsigned num_backends = ctx->screen->info.r600_num_backends;
unsigned i, mask = 0;
+ uint64_t va;
/* if backend_map query is supported by the kernel */
if (ctx->screen->info.r600_backend_map_valid) {
if (!buffer)
goto err;
+ va = r600_resource_va(&ctx->screen->screen, (void*)buffer);
+
/* initialize buffer with zeroes */
- results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
+ results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
if (results) {
memset(results, 0, ctx->max_db * 4 * 4);
- ctx->ws->buffer_unmap(buffer->buf);
+ ctx->ws->buffer_unmap(buffer->cs_buf);
/* emit EVENT_WRITE for ZPASS_DONE */
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1);
- cs->buf[cs->cdw++] = 0;
- cs->buf[cs->cdw++] = 0;
+ cs->buf[cs->cdw++] = va;
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE);
/* analyze results */
- results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ);
+ results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ);
if (results) {
for(i = 0; i < ctx->max_db; i++) {
/* at least highest bit will be set if backend is used */
if (results[i*4 + 1])
mask |= (1<<i);
}
- ctx->ws->buffer_unmap(buffer->buf);
+ ctx->ws->buffer_unmap(buffer->cs_buf);
}
}
int j, n = nreg;
/* initialize block */
- if (opcode == PKT3_SET_RESOURCE) {
- block->flags = BLOCK_FLAG_RESOURCE;
- block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */
- } else {
- block->flags = 0;
- block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
- }
+ block->flags = 0;
+ block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
block->start_offset = reg[i].offset;
block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
static const struct r600_reg r600_config_reg_list[] = {
{R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
- {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
};
static const struct r600_reg r600_ctl_const_list[] = {
{R_028124_CB_CLEAR_GREEN, 0, 0},
{R_028128_CB_CLEAR_BLUE, 0, 0},
{R_02812C_CB_CLEAR_ALPHA, 0, 0},
- {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0},
- {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0},
- {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0},
- {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0},
- {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0},
- {R_02823C_CB_SHADER_MASK, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
- {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0},
{R_028414_CB_BLEND_RED, 0, 0},
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_02842C_CB_FOG_BLUE, 0, 0},
{R_028430_DB_STENCILREFMASK, 0, 0},
{R_028434_DB_STENCILREFMASK_BF, 0, 0},
- {R_028438_SX_ALPHA_REF, 0, 0},
{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
{R_0287A0_CB_SHADER_CONTROL, 0, 0},
{R_028800_DB_DEPTH_CONTROL, 0, 0},
{R_028804_CB_BLEND_CONTROL, 0, 0},
- {R_028808_CB_COLOR_CONTROL, 0, 0},
{R_02880C_DB_SHADER_CONTROL, 0, 0},
{R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH},
{R_028000_DB_DEPTH_SIZE, 0, 0},
{R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
+ {R_028D44_DB_ALPHA_TO_MASK, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028E74_PA_CL_UCP5_Y, 0, 0},
{R_028E78_PA_CL_UCP5_Z, 0, 0},
{R_028E7C_PA_CL_UCP5_W, 0, 0},
+ {R_028350_SX_MISC, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
{R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
};
-/* SHADER RESOURCE R600/R700 */
-int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base)
-{
- int i;
- struct r600_block *block;
- range->blocks = calloc(nblocks, sizeof(struct r600_block *));
- if (range->blocks == NULL)
- return -ENOMEM;
-
- reg[0].offset += offset;
- for (i = 0; i < nblocks; i++) {
- block = calloc(1, sizeof(struct r600_block));
- if (block == NULL) {
- return -ENOMEM;
- }
- ctx->nblocks++;
- range->blocks[i] = block;
- r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base);
-
- reg[0].offset += stride;
- }
- return 0;
-}
-
-
-static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride)
-{
- struct r600_reg r600_shader_resource[] = {
- {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0},
- {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0},
- {R_038008_RESOURCE0_WORD2, 0, 0},
- {R_03800C_RESOURCE0_WORD3, 0, 0},
- {R_038010_RESOURCE0_WORD4, 0, 0},
- {R_038014_RESOURCE0_WORD5, 0, 0},
- {R_038018_RESOURCE0_WORD6, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_resource);
-
- return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET);
-}
-
-/* SHADER SAMPLER R600/R700/EG/CM */
-int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
-{
- struct r600_reg r600_shader_sampler[] = {
- {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0},
- {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
- {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler);
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler[i].offset += offset;
- }
- return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
-}
-
-/* SHADER SAMPLER BORDER R600/R700 */
-static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
-{
- struct r600_reg r600_shader_sampler_border[] = {
- {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
- {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
- {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
- {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler_border);
-
- for (int i = 0; i < nreg; i++) {
- r600_shader_sampler_border[i].offset += offset;
- }
- return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
-}
-
static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
}
-static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks)
-{
- struct r600_block *block;
- int i;
-
- if (!range->blocks) {
- return; /* nothing to do */
- }
-
- for (i = 0; i < nblocks; i++) {
- block = range->blocks[i];
- if (block) {
- for (int k = 1; k <= block->nbo; k++)
- pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL);
- free(block);
- }
- }
- free(range->blocks);
-}
-
/* initialize */
void r600_context_fini(struct r600_context *ctx)
{
free(ctx->range[i].blocks);
}
}
- r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources);
- r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources);
- r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources);
free(ctx->blocks);
}
-static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index)
-{
- int c = *index;
- for (int j = 0; j < num_blocks; j++) {
- if (!range->blocks[j])
- continue;
-
- ctx->blocks[c++] = range->blocks[j];
- }
- *index = c;
-}
-
int r600_setup_block_table(struct r600_context *ctx)
{
/* setup block table */
}
}
}
-
- r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c);
- r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c);
- r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c);
return 0;
}
if (r)
goto out_err;
- /* PS SAMPLER BORDER */
- for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) {
- r = r600_state_sampler_border_init(ctx, offset);
- if (r)
- goto out_err;
- }
-
- /* VS SAMPLER BORDER */
- for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) {
- r = r600_state_sampler_border_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* PS SAMPLER */
- for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER */
- for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
-
- ctx->num_ps_resources = 160;
- ctx->num_vs_resources = 160;
- ctx->num_fs_resources = 16;
- r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c);
- if (r)
- goto out_err;
- r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c);
- if (r)
- goto out_err;
- r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c);
- if (r)
- goto out_err;
-
/* PS loop const */
r600_loop_const_init(ctx, 0);
/* VS loop const */
}
}
+/**
+ * If reg needs a reloc, this function will add it to its block's reloc list.
+ * @return true if reg needs a reloc, false otherwise
+ */
+static bool r600_reg_set_block_reloc(struct r600_pipe_reg *reg)
+{
+ unsigned reloc_id;
+
+ if (!reg->block->pm4_bo_index[reg->id]) {
+ return false;
+ }
+ /* find relocation */
+ reloc_id = reg->block->pm4_bo_index[reg->id];
+ pipe_resource_reference(
+ (struct pipe_resource**)®->block->reloc[reloc_id].bo,
+ ®->bo->b.b);
+ reg->block->reloc[reloc_id].bo_usage = reg->bo_usage;
+ return true;
+}
+
+/**
+ * This function will emit all the registers in state directly to the command
+ * stream allowing you to bypass the r600_context dirty list.
+ *
+ * This is used for dispatching compute shaders to avoid mixing compute and
+ * 3D states in the context's dirty list.
+ *
+ * @param pkt_flags Should be either 0 or RADEON_CP_PACKET3_COMPUTE_MODE. This
+ * value will be passed on to r600_context_block_emit_dirty an or'd against
+ * the PKT3 headers.
+ */
+void r600_context_pipe_state_emit(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ unsigned pkt_flags)
+{
+ unsigned i;
+
+ /* Mark all blocks as dirty:
+ * Since two registers can be in the same block, we need to make sure
+ * we mark all the blocks dirty before we emit any of them. If we were
+ * to mark blocks dirty and emit them in the same loop, like this:
+ *
+ * foreach (reg in state->regs) {
+ * mark_dirty(reg->block)
+ * emit_block(reg->block)
+ * }
+ *
+ * Then if we have two registers in this state that are in the same
+ * block, we would end up emitting that block twice.
+ */
+ for (i = 0; i < state->nregs; i++) {
+ struct r600_pipe_reg *reg = &state->regs[i];
+ /* Mark all the registers in the block as dirty */
+ reg->block->nreg_dirty = reg->block->nreg;
+ reg->block->status |= R600_BLOCK_STATUS_DIRTY;
+ /* Update the reloc for this register if necessary. */
+ r600_reg_set_block_reloc(reg);
+ }
+
+ /* Emit the registers writes */
+ for (i = 0; i < state->nregs; i++) {
+ struct r600_pipe_reg *reg = &state->regs[i];
+ if (reg->block->status & R600_BLOCK_STATUS_DIRTY) {
+ r600_context_block_emit_dirty(ctx, reg->block, pkt_flags);
+ }
+ }
+}
+
void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state)
{
struct r600_block *block;
int dirty;
for (int i = 0; i < state->nregs; i++) {
- unsigned id, reloc_id;
+ unsigned id;
struct r600_pipe_reg *reg = &state->regs[i];
block = reg->block;
}
if (block->flags & REG_FLAG_DIRTY_ALWAYS)
dirty |= R600_BLOCK_STATUS_DIRTY;
- if (block->pm4_bo_index[id]) {
- /* find relocation */
- reloc_id = block->pm4_bo_index[id];
- pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, ®->bo->b.b.b);
- block->reloc[reloc_id].bo_usage = reg->bo_usage;
+ if (r600_reg_set_block_reloc(reg)) {
/* always force dirty for relocs for now */
dirty |= R600_BLOCK_STATUS_DIRTY;
}
}
}
-static void r600_context_dirty_resource_block(struct r600_context *ctx,
- struct r600_block *block,
- int dirty, int index)
-{
- block->nreg_dirty = index + 1;
-
- if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) {
- block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
- ctx->pm4_dirty_cdwords += block->pm4_ndwords;
- if (!(block->status & R600_BLOCK_STATUS_ENABLED)) {
- block->status |= R600_BLOCK_STATUS_ENABLED;
- LIST_ADDTAIL(&block->enable_list, &ctx->enable_list);
- }
- LIST_ADDTAIL(&block->list,&ctx->resource_dirty);
- }
-}
-
-void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block)
-{
- int dirty;
- int num_regs = ctx->chip_class >= EVERGREEN ? 8 : 7;
- boolean is_vertex;
-
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY);
- pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL);
- pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
-
- is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000);
- dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY;
-
- if (memcmp(block->reg, state->val, num_regs*4)) {
- memcpy(block->reg, state->val, num_regs * 4);
- dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
- }
-
- /* if no BOs on block, force dirty */
- if (!block->reloc[1].bo || !block->reloc[2].bo)
- dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
-
- if (!dirty) {
- if (is_vertex) {
- if (block->reloc[1].bo->buf != state->bo[0]->buf)
- dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
- } else {
- if ((block->reloc[1].bo->buf != state->bo[0]->buf) ||
- (block->reloc[2].bo->buf != state->bo[1]->buf))
- dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
- }
- }
-
- if (dirty) {
- if (is_vertex) {
- /* VERTEX RESOURCE, we preted there is 2 bo to relocate so
- * we have single case btw VERTEX & TEXTURE resource
- */
- pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
- block->reloc[1].bo_usage = state->bo_usage[0];
- pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL);
- } else {
- /* TEXTURE RESOURCE */
- pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b);
- block->reloc[1].bo_usage = state->bo_usage[0];
- pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b);
- block->reloc[2].bo_usage = state->bo_usage[1];
- }
-
- if (is_vertex)
- block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX;
- else
- block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX;
-
- r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1);
- }
-}
-
-void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
-{
- struct r600_block *block = ctx->ps_resources.blocks[rid];
-
- r600_context_pipe_state_set_resource(ctx, state, block);
-}
-
-void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
-{
- struct r600_block *block = ctx->vs_resources.blocks[rid];
-
- r600_context_pipe_state_set_resource(ctx, state, block);
-}
-
-void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid)
-{
- struct r600_block *block = ctx->fs_resources.blocks[rid];
-
- r600_context_pipe_state_set_resource(ctx, state, block);
-}
-
-void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
-{
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(offset)];
- block = range->blocks[CTX_BLOCK_ID(offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
-
- for (i = 0; i < 3; i++) {
- if (block->reg[i] != state->regs[i].value) {
- block->reg[i] = state->regs[i].value;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
- }
-
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 2);
-}
-
-static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset)
-{
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = &ctx->range[CTX_RANGE_ID(offset)];
- block = range->blocks[CTX_BLOCK_ID(offset)];
- if (state == NULL) {
- block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(&block->list);
- LIST_DELINIT(&block->enable_list);
- return;
- }
- if (state->nregs <= 3) {
- return;
- }
- dirty = block->status & R600_BLOCK_STATUS_DIRTY;
- for (i = 0; i < 4; i++) {
- if (block->reg[i] != state->regs[i + 3].value) {
- block->reg[i] = state->regs[i + 3].value;
- dirty |= R600_BLOCK_STATUS_DIRTY;
- }
- }
-
- /* We have to flush the shaders before we change the border color
- * registers, or previous draw commands that haven't completed yet
- * will end up using the new border color. */
- if (dirty & R600_BLOCK_STATUS_DIRTY)
- r600_context_ps_partial_flush(ctx);
- if (dirty)
- r600_context_dirty_block(ctx, block, dirty, 3);
-}
-
-void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id;
- r600_context_pipe_state_set_sampler(ctx, state, offset);
- offset = R_00A400_TD_PS_SAMPLER0_BORDER_RED + 16*id;
- r600_context_pipe_state_set_sampler_border(ctx, state, offset);
-}
-
-void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id)
-{
- unsigned offset;
-
- offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18);
- r600_context_pipe_state_set_sampler(ctx, state, offset);
- offset = R_00A600_TD_VS_SAMPLER0_BORDER_RED + 16*id;
- r600_context_pipe_state_set_sampler_border(ctx, state, offset);
-}
-
-void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block)
+/**
+ * @param pkt_flags should be set to RADEON_CP_PACKET3_COMPUTE_MODE if this
+ * block will be used for compute shaders.
+ */
+void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block,
+ unsigned pkt_flags)
{
struct radeon_winsys_cs *cs = ctx->cs;
int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS);
cp_dwords = new_dwords + 2;
}
memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
+
+ /* We are applying the pkt_flags after copying the register block to
+ * the the command stream, because it is possible this block will be
+ * emitted with a different pkt_flags, and we don't want to store the
+ * pkt_flags in the block.
+ */
+ cs->buf[cs->cdw] |= pkt_flags;
cs->cdw += cp_dwords;
if (optional) {
LIST_DELINIT(&block->list);
}
-void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
- int cp_dwords = block->pm4_ndwords;
- int nbo = block->nbo;
-
- if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) {
- nbo = 1;
- cp_dwords -= 2; /* don't copy the second NOP */
- }
-
- for (int j = 0; j < nbo; j++) {
- if (block->pm4_bo_index[j]) {
- /* find relocation */
- struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]];
- block->pm4[reloc->bo_pm4_index] =
- r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage);
- }
- }
-
- memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4);
- cs->cdw += cp_dwords;
-
- block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY;
- block->nreg_dirty = 0;
- LIST_DELINIT(&block->list);
-}
-
void r600_inval_shader_cache(struct r600_context *ctx)
{
ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1);
void r600_inval_vertex_cache(struct r600_context *ctx)
{
- if (ctx->family == CHIP_RV610 ||
- ctx->family == CHIP_RV620 ||
- ctx->family == CHIP_RS780 ||
- ctx->family == CHIP_RS880 ||
- ctx->family == CHIP_RV710 ||
- ctx->family == CHIP_CEDAR ||
- ctx->family == CHIP_PALM ||
- ctx->family == CHIP_SUMO ||
- ctx->family == CHIP_SUMO2 ||
- ctx->family == CHIP_CAICOS ||
- ctx->family == CHIP_CAYMAN) {
+ if (ctx->has_vertex_cache) {
+ ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
+ } else {
/* Some GPUs don't have the vertex cache and must use the texture cache instead. */
ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
- } else {
- ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
}
r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
}
r600_flush_framebuffer(ctx, true);
/* partial flush is needed to avoid lockups on some chips with user fences */
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+ r600_context_ps_partial_flush(ctx);
+
+ /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
+ if (ctx->chip_class <= R700) {
+ r600_write_context_reg(cs, R_028350_SX_MISC, 0);
+ }
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
+ /* Begin a new CS. */
r600_emit_atom(ctx, &ctx->start_cs_cmd.atom);
+
+ /* Invalidate caches. */
+ r600_inval_texture_cache(ctx);
+ r600_flush_framebuffer(ctx, false);
+
+ /* Re-emit states. */
+ r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
+ r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
+ /* reemit sampler, will only matter if atom_sampler.num_dw != 0 */
+ r600_atom_dirty(ctx, &ctx->vs_samplers.atom_sampler);
+ r600_atom_dirty(ctx, &ctx->ps_samplers.atom_sampler);
+ if (ctx->chip_class <= R700) {
+ r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
+ }
+ r600_atom_dirty(ctx, &ctx->sample_mask.atom);
+
+ ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
+ r600_vertex_buffers_dirty(ctx);
+
+ ctx->vs_constbuf_state.dirty_mask = ctx->vs_constbuf_state.enabled_mask;
+ ctx->ps_constbuf_state.dirty_mask = ctx->ps_constbuf_state.enabled_mask;
+ r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state);
+ r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state);
+
+ ctx->vs_samplers.views.dirty_mask = ctx->vs_samplers.views.enabled_mask;
+ ctx->ps_samplers.views.dirty_mask = ctx->ps_samplers.views.enabled_mask;
+ r600_sampler_views_dirty(ctx, &ctx->vs_samplers.views);
+ r600_sampler_views_dirty(ctx, &ctx->ps_samplers.views);
if (streamout_suspended) {
ctx->streamout_start = TRUE;
* next draw command
*/
LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) {
- if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) {
- if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
- LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
- enable_block->status |= R600_BLOCK_STATUS_DIRTY;
- }
- } else {
- if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) {
- LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty);
- enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY;
- }
+ if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) {
+ LIST_ADDTAIL(&enable_block->list,&ctx->dirty);
+ enable_block->status |= R600_BLOCK_STATUS_DIRTY;
}
ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
enable_block->nreg_dirty = enable_block->nreg;
va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
va = va + (offset << 2);
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+ r600_context_ps_partial_flush(ctx);
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
ctx->num_cs_dw_streamout_end =
12 + /* flush_vgt_streamout */
- util_bitcount(buffer_en) * 8 +
- 3;
+ util_bitcount(buffer_en) * 8 + /* STRMOUT_BUFFER_UPDATE */
+ 3 /* set_streamout_enable(0) */;
r600_need_cs_space(ctx,
12 + /* flush_vgt_streamout */
- 6 + /* enables */
- util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 +
- util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 +
- (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) +
+ 6 + /* set_streamout_enable */
+ util_bitcount(buffer_en) * 7 + /* SET_CONTEXT_REG */
+ (ctx->chip_class == R700 ? util_bitcount(buffer_en) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
+ util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
+ util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
+ (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
ctx->num_cs_dw_streamout_end, TRUE);
if (ctx->chip_class >= EVERGREEN) {
r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
RADEON_USAGE_WRITE);
+ /* R7xx requires this packet after updating BUFFER_BASE.
+ * Without this, R7xx locks up. */
+ if (ctx->chip_class == R700) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BASE_UPDATE, 1, 0);
+ cs->buf[cs->cdw++] = i;
+ cs->buf[cs->cdw++] = va >> 8;
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] =
+ r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer),
+ RADEON_USAGE_WRITE);
+ }
+
if (ctx->streamout_append_bitmask & (1 << i)) {
va = r600_resource_va(&ctx->screen->screen,
(void*)t[i]->filled_size);
}
/* Flush streamout caches. */
- ctx->surface_sync_cmd.flush_flags |= flush_flags;
+ ctx->surface_sync_cmd.flush_flags |=
+ S_0085F0_SMX_ACTION_ENA(1) | flush_flags;
r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
ctx->num_cs_dw_streamout_end = 0;
-
-#if 0
- for (i = 0; i < ctx->num_so_targets; i++) {
- if (!t[i])
- continue;
-
- uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ);
- printf("FILLED_SIZE%i: %u\n", i, *ptr);
- ctx->ws->buffer_unmap(t[i]->filled_size->buf);
- }
-#endif
-}
-
-void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
- uint64_t va = r600_resource_va(&ctx->screen->screen,
- (void*)t->filled_size);
-
- r600_need_cs_space(ctx, 14 + 21, TRUE);
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = 0;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
- cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2;
- cs->buf[cs->cdw++] = t->stride_in_dw;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
- cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
- cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
- cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
- cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
- cs->buf[cs->cdw++] = 0; /* unused */
-
- cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ);
}
projects / mesa.git / blobdiff