if (!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs, ctx->b.vram, ctx->b.gtt)) {
ctx->b.gtt = 0;
ctx->b.vram = 0;
- ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+ ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
return;
}
/* all will be accounted once relocation are emited */
}
/* SX_MISC */
- if (ctx->b.chip_class <= R700) {
+ if (ctx->b.chip_class == R600) {
num_dw += 3;
}
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
- ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+ ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
}
}
S_0085F0_SMX_ACTION_ENA(1);
}
+ /* Workaround for buggy flushing on some R6xx chipsets. */
+ if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV &&
+ (rctx->b.family == CHIP_RV670 ||
+ rctx->b.family == CHIP_RS780 ||
+ rctx->b.family == CHIP_RS880)) {
+ cp_coher_cntl |= S_0085F0_CB1_DEST_BASE_ENA(1) |
+ S_0085F0_DEST_BASE_0_ENA(1);
+ }
+
if (cp_coher_cntl) {
cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */
rctx->b.flags = 0;
}
-void r600_context_flush(struct r600_context *ctx, unsigned flags)
+void r600_context_gfx_flush(void *context, unsigned flags,
+ struct pipe_fence_handle **fence)
{
+ struct r600_context *ctx = context;
struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs;
- ctx->b.nontimer_queries_suspended = false;
- ctx->b.streamout.suspended = false;
+ if (cs->cdw == ctx->b.initial_gfx_cs_size && !fence)
+ return;
- /* suspend queries */
- if (ctx->b.num_cs_dw_nontimer_queries_suspend) {
- r600_suspend_nontimer_queries(&ctx->b);
- ctx->b.nontimer_queries_suspended = true;
- }
+ ctx->b.rings.gfx.flushing = true;
- if (ctx->b.streamout.begin_emitted) {
- r600_emit_streamout_end(&ctx->b);
- ctx->b.streamout.suspended = true;
- }
+ r600_preflush_suspend_features(&ctx->b);
/* flush the framebuffer cache */
ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV |
r600_flush_emit(ctx);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
- if (ctx->b.chip_class <= R700) {
+ if (ctx->b.chip_class == R600) {
r600_write_context_reg(cs, R_028350_SX_MISC, 0);
}
}
/* Flush the CS. */
- ctx->b.ws->cs_flush(ctx->b.rings.gfx.cs, flags, ctx->screen->b.cs_count++);
+ ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++);
+ ctx->b.rings.gfx.flushing = false;
+
+ r600_begin_new_cs(ctx);
}
void r600_begin_new_cs(struct r600_context *ctx)
r600_sampler_states_dirty(ctx, &samplers->states);
}
- if (ctx->b.streamout.suspended) {
- ctx->b.streamout.append_bitmask = ctx->b.streamout.enabled_mask;
- r600_streamout_buffers_dirty(&ctx->b);
- }
-
- /* resume queries */
- if (ctx->b.nontimer_queries_suspended) {
- r600_resume_nontimer_queries(&ctx->b);
- }
+ r600_postflush_resume_features(&ctx->b);
/* Re-emit the draw state. */
ctx->last_primitive_type = -1;