r600g: Close a memory leak of llvm byte streams
[mesa.git] / src / gallium / drivers / r600 / r600_hw_context.c
index 7cf17d0b4d1ee710ec497281ea071c2049fccc0a..e9369de90c01f38061eec628e2b71ade549ce8ca 100644 (file)
@@ -226,7 +226,6 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 
 /* R600/R700 configuration */
 static const struct r600_reg r600_config_reg_list[] = {
-       {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
        {R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, 0, 0},
        {R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, 0, 0},
        {R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 0, 0},
@@ -234,10 +233,6 @@ static const struct r600_reg r600_config_reg_list[] = {
        {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
 };
 
-static const struct r600_reg r600_ctl_const_list[] = {
-       {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
 static const struct r600_reg r600_context_reg_list[] = {
        {R_028A4C_PA_SC_MODE_CNTL, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
@@ -348,7 +343,6 @@ static const struct r600_reg r600_context_reg_list[] = {
        {R_028004_DB_DEPTH_VIEW, 0, 0},
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
-       {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
        {R_028D24_DB_HTILE_SURFACE, 0, 0},
        {R_028D34_DB_PREFETCH_LIMIT, 0, 0},
        {R_028D44_DB_ALPHA_TO_MASK, 0, 0},
@@ -357,13 +351,10 @@ static const struct r600_reg r600_context_reg_list[] = {
        {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
        {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
        {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
-       {R_028810_PA_CL_CLIP_CNTL, 0, 0},
        {R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
-       {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
        {R_028A00_PA_SU_POINT_SIZE, 0, 0},
        {R_028A04_PA_SU_POINT_MINMAX, 0, 0},
        {R_028A08_PA_SU_LINE_CNTL, 0, 0},
-       {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
        {R_028C00_PA_SC_LINE_CNTL, 0, 0},
        {R_028C04_PA_SC_AA_CONFIG, 0, 0},
        {R_028C08_PA_SU_VTX_CNTL, 0, 0},
@@ -466,9 +457,6 @@ static const struct r600_reg r600_context_reg_list[] = {
        {GROUP_FORCE_NEW_BLOCK, 0, 0},
        {R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
        {R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
-       {R_028408_VGT_INDX_OFFSET, 0, 0},
-       {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
-       {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
        {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
        {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
 };
@@ -560,10 +548,6 @@ int r600_context_init(struct r600_context *ctx)
                                   Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
        if (r)
                goto out_err;
-       r = r600_context_add_block(ctx, r600_ctl_const_list,
-                                  Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
-       if (r)
-               goto out_err;
 
        /* PS loop const */
        r600_loop_const_init(ctx, 0);
@@ -599,8 +583,8 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
 
                num_dw += ctx->pm4_dirty_cdwords;
 
-               /* The upper-bound of how much a draw command would take. */
-               num_dw += R600_MAX_DRAW_CS_DWORDS;
+               /* The upper-bound of how much space a draw command would take. */
+               num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
        }
 
        /* Count in queries_suspend. */
@@ -615,11 +599,16 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
                num_dw += 3;
        }
 
+       /* SX_MISC */
+       if (ctx->chip_class <= R700) {
+               num_dw += 3;
+       }
+
        /* Count in framebuffer cache flushes at the end of CS. */
-       num_dw += 44; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
+       num_dw += R600_MAX_FLUSH_CS_DWORDS;
 
-       /* Save 16 dwords for the fence mechanism. */
-       num_dw += 16;
+       /* The fence at the end of CS. */
+       num_dw += 10;
 
        /* Flush if there's not enough space. */
        if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
@@ -1014,8 +1003,11 @@ void r600_begin_new_cs(struct r600_context *ctx)
        r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
        r600_atom_dirty(ctx, &ctx->blend_color.atom);
        r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
+       r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
        r600_atom_dirty(ctx, &ctx->clip_state.atom);
        r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
+       r600_atom_dirty(ctx, &ctx->vgt_state.atom);
+       r600_atom_dirty(ctx, &ctx->vgt2_state.atom);
        r600_atom_dirty(ctx, &ctx->sample_mask.atom);
        r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
        r600_atom_dirty(ctx, &ctx->viewport.atom);
@@ -1065,6 +1057,10 @@ void r600_begin_new_cs(struct r600_context *ctx)
                ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
                enable_block->nreg_dirty = enable_block->nreg;
        }
+
+       /* Re-emit the draw state. */
+       ctx->last_primitive_type = -1;
+       ctx->last_start_instance = -1;
 }
 
 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)