return;
}
-void r600_context_ps_partial_flush(struct r600_context *ctx)
-{
- struct radeon_winsys_cs *cs = ctx->cs;
-
- if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING))
- return;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
-
- ctx->flags &= ~R600_CONTEXT_DRAW_PENDING;
-}
-
static void r600_init_block(struct r600_context *ctx,
struct r600_block *block,
const struct r600_reg *reg, int index, int nreg,
/* R600/R700 configuration */
static const struct r600_reg r600_config_reg_list[] = {
- {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
+ {R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, 0, 0},
+ {R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, 0, 0},
+ {R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 0, 0},
+ {R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, 0, 0},
{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
};
-static const struct r600_reg r600_ctl_const_list[] = {
- {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
static const struct r600_reg r600_context_reg_list[] = {
{R_028A4C_PA_SC_MODE_CNTL, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
+ {R_028100_CB_COLOR0_MASK, 0, 0},
{R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0},
{R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0},
+ {R_028104_CB_COLOR1_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0},
+ {R_028108_CB_COLOR2_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0},
+ {R_02810C_CB_COLOR3_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0},
+ {R_028110_CB_COLOR4_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0},
+ {R_028114_CB_COLOR5_MASK, 0, 0},
{R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)},
{R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0},
{R_028078_CB_COLOR6_SIZE, 0, 0},
{R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0},
+ {R_028118_CB_COLOR6_MASK, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_02809C_CB_COLOR7_VIEW, 0, 0},
{R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0},
{R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0},
+ {R_02811C_CB_COLOR7_MASK, 0, 0},
{R_028120_CB_CLEAR_RED, 0, 0},
{R_028124_CB_CLEAR_GREEN, 0, 0},
{R_028128_CB_CLEAR_BLUE, 0, 0},
{R_02812C_CB_CLEAR_ALPHA, 0, 0},
- {R_028414_CB_BLEND_RED, 0, 0},
- {R_028418_CB_BLEND_GREEN, 0, 0},
- {R_02841C_CB_BLEND_BLUE, 0, 0},
- {R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028424_CB_FOG_RED, 0, 0},
{R_028428_CB_FOG_GREEN, 0, 0},
{R_02842C_CB_FOG_BLUE, 0, 0},
- {R_028430_DB_STENCILREFMASK, 0, 0},
- {R_028434_DB_STENCILREFMASK_BF, 0, 0},
{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028004_DB_DEPTH_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
- {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
{R_028D44_DB_ALPHA_TO_MASK, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
- {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
- {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
- {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
- {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
- {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
- {R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
- {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
+ {R_028C00_PA_SC_LINE_CNTL, 0, 0},
+ {R_028C04_PA_SC_AA_CONFIG, 0, 0},
{R_028C08_PA_SU_VTX_CNTL, 0, 0},
{R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0},
{R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0},
{R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
{R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
{R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
- {R_028E20_PA_CL_UCP0_X, 0, 0},
- {R_028E24_PA_CL_UCP0_Y, 0, 0},
- {R_028E28_PA_CL_UCP0_Z, 0, 0},
- {R_028E2C_PA_CL_UCP0_W, 0, 0},
- {R_028E30_PA_CL_UCP1_X, 0, 0},
- {R_028E34_PA_CL_UCP1_Y, 0, 0},
- {R_028E38_PA_CL_UCP1_Z, 0, 0},
- {R_028E3C_PA_CL_UCP1_W, 0, 0},
- {R_028E40_PA_CL_UCP2_X, 0, 0},
- {R_028E44_PA_CL_UCP2_Y, 0, 0},
- {R_028E48_PA_CL_UCP2_Z, 0, 0},
- {R_028E4C_PA_CL_UCP2_W, 0, 0},
- {R_028E50_PA_CL_UCP3_X, 0, 0},
- {R_028E54_PA_CL_UCP3_Y, 0, 0},
- {R_028E58_PA_CL_UCP3_Z, 0, 0},
- {R_028E5C_PA_CL_UCP3_W, 0, 0},
- {R_028E60_PA_CL_UCP4_X, 0, 0},
- {R_028E64_PA_CL_UCP4_Y, 0, 0},
- {R_028E68_PA_CL_UCP4_Z, 0, 0},
- {R_028E6C_PA_CL_UCP4_W, 0, 0},
- {R_028E70_PA_CL_UCP5_X, 0, 0},
- {R_028E74_PA_CL_UCP5_Y, 0, 0},
- {R_028E78_PA_CL_UCP5_Z, 0, 0},
- {R_028E7C_PA_CL_UCP5_W, 0, 0},
{R_028350_SX_MISC, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
{R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
- {R_028408_VGT_INDX_OFFSET, 0, 0},
- {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
- {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
+ {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
+ {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
};
static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
if (r)
goto out_err;
- r = r600_context_add_block(ctx, r600_ctl_const_list,
- Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
- if (r)
- goto out_err;
/* PS loop const */
r600_loop_const_init(ctx, 0);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
- struct r600_atom *state;
-
/* The number of dwords we already used in the CS so far. */
num_dw += ctx->cs->cdw;
if (count_draw_in) {
+ unsigned i;
+
/* The number of dwords all the dirty states would take. */
- LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) {
- num_dw += state->num_dw;
+ for (i = 0; i < R600_NUM_ATOMS; i++) {
+ if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
+ num_dw += ctx->atoms[i]->num_dw;
+ }
}
num_dw += ctx->pm4_dirty_cdwords;
- /* The upper-bound of how much a draw command would take. */
- num_dw += R600_MAX_DRAW_CS_DWORDS;
+ /* The upper-bound of how much space a draw command would take. */
+ num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
}
/* Count in queries_suspend. */
num_dw += 3;
}
+ /* SX_MISC */
+ if (ctx->chip_class <= R700) {
+ num_dw += 3;
+ }
+
/* Count in framebuffer cache flushes at the end of CS. */
- num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
+ num_dw += R600_MAX_FLUSH_CS_DWORDS;
- /* Save 16 dwords for the fence mechanism. */
- num_dw += 16;
+ /* The fence at the end of CS. */
+ num_dw += 10;
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
LIST_ADDTAIL(&block->list,&ctx->dirty);
if (block->flags & REG_FLAG_FLUSH_CHANGE) {
- r600_context_ps_partial_flush(ctx);
+ ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
}
}
}
LIST_DELINIT(&block->list);
}
-void r600_inval_shader_cache(struct r600_context *ctx)
+void r600_flush_emit(struct r600_context *rctx)
{
- ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1);
- r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
-}
+ struct radeon_winsys_cs *cs = rctx->cs;
-void r600_inval_texture_cache(struct r600_context *ctx)
-{
- ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
- r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
-}
+ if (!rctx->flags) {
+ return;
+ }
-void r600_inval_vertex_cache(struct r600_context *ctx)
-{
- if (ctx->has_vertex_cache) {
- ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1);
- } else {
- /* Some GPUs don't have the vertex cache and must use the texture cache instead. */
- ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1);
+ if (rctx->flags & R600_CONTEXT_PS_PARTIAL_FLUSH) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+ cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
}
- r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
-}
-void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now)
-{
- if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
- return;
+ if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+ cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
+
+ /* DB flushes are special due to errata with hyperz, we need to
+ * insert a no-op, so that the cache has time to really flush.
+ */
+ if (rctx->chip_class <= R700 &&
+ rctx->flags & R600_CONTEXT_HTILE_ERRATA) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 31, 0);
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ cs->buf[cs->cdw++] = 0xdeadcafe;
+ }
+ }
- ctx->surface_sync_cmd.flush_flags |=
- r600_get_cb_flush_flags(ctx) |
- (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0);
+ if (rctx->flags & (R600_CONTEXT_CB_FLUSH |
+ R600_CONTEXT_DB_FLUSH |
+ R600_CONTEXT_SHADERCONST_FLUSH |
+ R600_CONTEXT_TEX_FLUSH |
+ R600_CONTEXT_VTX_FLUSH |
+ R600_CONTEXT_STREAMOUT_FLUSH)) {
+ /* anything left (cb, vtx, shader, streamout) can be flushed
+ * using the surface sync packet
+ */
+ unsigned flags = 0;
+
+ if (rctx->flags & R600_CONTEXT_CB_FLUSH) {
+ flags |= S_0085F0_CB_ACTION_ENA(1) |
+ S_0085F0_CB0_DEST_BASE_ENA(1) |
+ S_0085F0_CB1_DEST_BASE_ENA(1) |
+ S_0085F0_CB2_DEST_BASE_ENA(1) |
+ S_0085F0_CB3_DEST_BASE_ENA(1) |
+ S_0085F0_CB4_DEST_BASE_ENA(1) |
+ S_0085F0_CB5_DEST_BASE_ENA(1) |
+ S_0085F0_CB6_DEST_BASE_ENA(1) |
+ S_0085F0_CB7_DEST_BASE_ENA(1);
+
+ if (rctx->chip_class >= EVERGREEN) {
+ flags |= S_0085F0_CB8_DEST_BASE_ENA(1) |
+ S_0085F0_CB9_DEST_BASE_ENA(1) |
+ S_0085F0_CB10_DEST_BASE_ENA(1) |
+ S_0085F0_CB11_DEST_BASE_ENA(1);
+ }
- if (flush_now) {
- r600_emit_atom(ctx, &ctx->surface_sync_cmd.atom);
- } else {
- r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
- }
+ /* RV670 errata
+ * (CB1_DEST_BASE_ENA is also required, which is
+ * included unconditionally above). */
+ if (rctx->family == CHIP_RV670 ||
+ rctx->family == CHIP_RS780 ||
+ rctx->family == CHIP_RS880) {
+ flags |= S_0085F0_DEST_BASE_0_ENA(1);
+ }
+ }
- /* Also add a complete cache flush to work around broken flushing on R6xx. */
- if (ctx->chip_class == R600) {
- if (flush_now) {
- r600_emit_atom(ctx, &ctx->r6xx_flush_and_inv_cmd);
- } else {
- r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
+ if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
+ flags |= S_0085F0_SO0_DEST_BASE_ENA(1) |
+ S_0085F0_SO1_DEST_BASE_ENA(1) |
+ S_0085F0_SO2_DEST_BASE_ENA(1) |
+ S_0085F0_SO3_DEST_BASE_ENA(1) |
+ S_0085F0_SMX_ACTION_ENA(1);
+
+ /* RV670 errata */
+ if (rctx->family == CHIP_RV670 ||
+ rctx->family == CHIP_RS780 ||
+ rctx->family == CHIP_RS880) {
+ flags |= S_0085F0_DEST_BASE_0_ENA(1);
+ }
}
+
+ flags |= (rctx->flags & R600_CONTEXT_DB_FLUSH) ? S_0085F0_DB_ACTION_ENA(1) |
+ S_0085F0_DB_DEST_BASE_ENA(1): 0;
+ flags |= (rctx->flags & R600_CONTEXT_SHADERCONST_FLUSH) ? S_0085F0_SH_ACTION_ENA(1) : 0;
+ flags |= (rctx->flags & R600_CONTEXT_TEX_FLUSH) ? S_0085F0_TC_ACTION_ENA(1) : 0;
+ flags |= (rctx->flags & R600_CONTEXT_VTX_FLUSH) ? S_0085F0_VC_ACTION_ENA(1) : 0;
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
+ cs->buf[cs->cdw++] = flags; /* CP_COHER_CNTL */
+ cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
+ cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
+ cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
+ }
+
+ if (rctx->flags & R600_CONTEXT_WAIT_IDLE) {
+ /* wait for things to settle */
+ r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
}
- ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
+ /* everything is properly flushed */
+ rctx->flags = 0;
}
void r600_context_flush(struct r600_context *ctx, unsigned flags)
{
struct radeon_winsys_cs *cs = ctx->cs;
- struct r600_block *enable_block = NULL;
- bool timer_queries_suspended = false;
- bool nontimer_queries_suspended = false;
- bool streamout_suspended = false;
if (cs->cdw == ctx->start_cs_cmd.atom.num_dw)
return;
+ ctx->timer_queries_suspended = false;
+ ctx->nontimer_queries_suspended = false;
+ ctx->streamout_suspended = false;
+
/* suspend queries */
if (ctx->num_cs_dw_timer_queries_suspend) {
r600_suspend_timer_queries(ctx);
- timer_queries_suspended = true;
+ ctx->timer_queries_suspended = true;
}
if (ctx->num_cs_dw_nontimer_queries_suspend) {
r600_suspend_nontimer_queries(ctx);
- nontimer_queries_suspended = true;
+ ctx->nontimer_queries_suspended = true;
}
if (ctx->num_cs_dw_streamout_end) {
r600_context_streamout_end(ctx);
- streamout_suspended = true;
+ ctx->streamout_suspended = true;
}
- r600_flush_framebuffer(ctx, true);
-
/* partial flush is needed to avoid lockups on some chips with user fences */
- r600_context_ps_partial_flush(ctx);
+ ctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+
+ /* flush the framebuffer */
+ ctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_DB_FLUSH;
+
+ /* R6xx errata */
+ if (ctx->chip_class == R600) {
+ ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
+ }
+
+ r600_flush_emit(ctx);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
if (ctx->chip_class <= R700) {
/* Flush the CS. */
ctx->ws->cs_flush(ctx->cs, flags);
+ r600_begin_new_cs(ctx);
+}
+
+void r600_begin_new_cs(struct r600_context *ctx)
+{
+ struct r600_block *enable_block = NULL;
+ unsigned shader;
+
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
/* Begin a new CS. */
r600_emit_atom(ctx, &ctx->start_cs_cmd.atom);
- /* Invalidate caches. */
- r600_inval_texture_cache(ctx);
- r600_flush_framebuffer(ctx, false);
-
/* Re-emit states. */
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
+ r600_atom_dirty(ctx, &ctx->blend_color.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
- /* reemit sampler, will only matter if atom_sampler.num_dw != 0 */
- r600_atom_dirty(ctx, &ctx->vs_samplers.atom_sampler);
- r600_atom_dirty(ctx, &ctx->ps_samplers.atom_sampler);
+ r600_atom_dirty(ctx, &ctx->vgt_state.atom);
+ r600_atom_dirty(ctx, &ctx->vgt2_state.atom);
+ r600_atom_dirty(ctx, &ctx->sample_mask.atom);
+ r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
+ r600_atom_dirty(ctx, &ctx->viewport.atom);
+
if (ctx->chip_class <= R700) {
r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
}
- r600_atom_dirty(ctx, &ctx->sample_mask.atom);
ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
r600_vertex_buffers_dirty(ctx);
- ctx->vs_constbuf_state.dirty_mask = ctx->vs_constbuf_state.enabled_mask;
- ctx->ps_constbuf_state.dirty_mask = ctx->ps_constbuf_state.enabled_mask;
- r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state);
- r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state);
+ /* Re-emit shader resources. */
+ for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
+ struct r600_constbuf_state *constbuf = &ctx->constbuf_state[shader];
+ struct r600_textures_info *samplers = &ctx->samplers[shader];
- ctx->vs_samplers.views.dirty_mask = ctx->vs_samplers.views.enabled_mask;
- ctx->ps_samplers.views.dirty_mask = ctx->ps_samplers.views.enabled_mask;
- r600_sampler_views_dirty(ctx, &ctx->vs_samplers.views);
- r600_sampler_views_dirty(ctx, &ctx->ps_samplers.views);
+ constbuf->dirty_mask = constbuf->enabled_mask;
+ samplers->views.dirty_mask = samplers->views.enabled_mask;
+ samplers->states.dirty_mask = samplers->states.enabled_mask;
+
+ r600_constant_buffers_dirty(ctx, constbuf);
+ r600_sampler_views_dirty(ctx, &samplers->views);
+ r600_sampler_states_dirty(ctx, &samplers->states);
+ }
- if (streamout_suspended) {
+ if (ctx->streamout_suspended) {
ctx->streamout_start = TRUE;
ctx->streamout_append_bitmask = ~0;
}
/* resume queries */
- if (timer_queries_suspended) {
+ if (ctx->timer_queries_suspended) {
r600_resume_timer_queries(ctx);
}
- if (nontimer_queries_suspended) {
+ if (ctx->nontimer_queries_suspended) {
r600_resume_nontimer_queries(ctx);
}
ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
enable_block->nreg_dirty = enable_block->nreg;
}
+
+ /* Re-emit the draw state. */
+ ctx->last_primitive_type = -1;
+ ctx->last_start_instance = -1;
}
void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
va = va + (offset << 2);
- r600_context_ps_partial_flush(ctx);
+ ctx->flags &= ~R600_CONTEXT_PS_PARTIAL_FLUSH;
+ cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+ cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
+
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */
{
struct radeon_winsys_cs *cs = ctx->cs;
struct r600_so_target **t = ctx->so_targets;
- unsigned i, flush_flags = 0;
+ unsigned i;
uint64_t va;
if (ctx->chip_class >= EVERGREEN) {
r600_context_bo_reloc(ctx, t[i]->filled_size,
RADEON_USAGE_WRITE);
- flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i;
}
}
} else {
r600_set_streamout_enable(ctx, 0);
}
+ ctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
- /* This is needed to fix cache flushes on r600. */
+ /* R6xx errata */
if (ctx->chip_class == R600) {
- if (ctx->family == CHIP_RV670 ||
- ctx->family == CHIP_RS780 ||
- ctx->family == CHIP_RS880) {
- flush_flags |= S_0085F0_DEST_BASE_0_ENA(1);
- }
-
- r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd);
+ ctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
}
-
- /* Flush streamout caches. */
- ctx->surface_sync_cmd.flush_flags |=
- S_0085F0_SMX_ACTION_ENA(1) | flush_flags;
- r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom);
-
ctx->num_cs_dw_streamout_end = 0;
}
projects / mesa.git / blobdiff