/* R600/R700 configuration */
static const struct r600_reg r600_config_reg_list[] = {
- {R_008958_VGT_PRIMITIVE_TYPE, 0, 0},
{R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, 0, 0},
{R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, 0, 0},
{R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 0, 0},
{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
};
-static const struct r600_reg r600_ctl_const_list[] = {
- {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
-};
-
static const struct r600_reg r600_context_reg_list[] = {
{R_028A4C_PA_SC_MODE_CNTL, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028124_CB_CLEAR_GREEN, 0, 0},
{R_028128_CB_CLEAR_BLUE, 0, 0},
{R_02812C_CB_CLEAR_ALPHA, 0, 0},
- {R_028414_CB_BLEND_RED, 0, 0},
- {R_028418_CB_BLEND_GREEN, 0, 0},
- {R_02841C_CB_BLEND_BLUE, 0, 0},
- {R_028420_CB_BLEND_ALPHA, 0, 0},
{R_028424_CB_FOG_RED, 0, 0},
{R_028428_CB_FOG_GREEN, 0, 0},
{R_02842C_CB_FOG_BLUE, 0, 0},
- {R_028430_DB_STENCILREFMASK, 0, 0},
- {R_028434_DB_STENCILREFMASK_BF, 0, 0},
{R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0},
{R_028004_DB_DEPTH_VIEW, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0},
- {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0},
{R_028D24_DB_HTILE_SURFACE, 0, 0},
{R_028D34_DB_PREFETCH_LIMIT, 0, 0},
{R_028D44_DB_ALPHA_TO_MASK, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
- {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
- {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
- {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
- {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
- {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
- {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
- {R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
- {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0},
{R_028A00_PA_SU_POINT_SIZE, 0, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{R_028A08_PA_SU_LINE_CNTL, 0, 0},
- {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0},
{R_028C00_PA_SC_LINE_CNTL, 0, 0},
{R_028C04_PA_SC_AA_CONFIG, 0, 0},
{R_028C08_PA_SU_VTX_CNTL, 0, 0},
{R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0},
{R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0},
{R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0},
- {R_028E20_PA_CL_UCP0_X, 0, 0},
- {R_028E24_PA_CL_UCP0_Y, 0, 0},
- {R_028E28_PA_CL_UCP0_Z, 0, 0},
- {R_028E2C_PA_CL_UCP0_W, 0, 0},
- {R_028E30_PA_CL_UCP1_X, 0, 0},
- {R_028E34_PA_CL_UCP1_Y, 0, 0},
- {R_028E38_PA_CL_UCP1_Z, 0, 0},
- {R_028E3C_PA_CL_UCP1_W, 0, 0},
- {R_028E40_PA_CL_UCP2_X, 0, 0},
- {R_028E44_PA_CL_UCP2_Y, 0, 0},
- {R_028E48_PA_CL_UCP2_Z, 0, 0},
- {R_028E4C_PA_CL_UCP2_W, 0, 0},
- {R_028E50_PA_CL_UCP3_X, 0, 0},
- {R_028E54_PA_CL_UCP3_Y, 0, 0},
- {R_028E58_PA_CL_UCP3_Z, 0, 0},
- {R_028E5C_PA_CL_UCP3_W, 0, 0},
- {R_028E60_PA_CL_UCP4_X, 0, 0},
- {R_028E64_PA_CL_UCP4_Y, 0, 0},
- {R_028E68_PA_CL_UCP4_Z, 0, 0},
- {R_028E6C_PA_CL_UCP4_W, 0, 0},
- {R_028E70_PA_CL_UCP5_X, 0, 0},
- {R_028E74_PA_CL_UCP5_Y, 0, 0},
- {R_028E78_PA_CL_UCP5_Z, 0, 0},
- {R_028E7C_PA_CL_UCP5_W, 0, 0},
{R_028350_SX_MISC, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028850_SQ_PGM_RESOURCES_PS, 0, 0},
{R_028854_SQ_PGM_EXPORTS_PS, 0, 0},
- {R_028408_VGT_INDX_OFFSET, 0, 0},
- {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0},
- {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0},
{R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0},
{R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0},
};
Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
if (r)
goto out_err;
- r = r600_context_add_block(ctx, r600_ctl_const_list,
- Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
- if (r)
- goto out_err;
/* PS loop const */
r600_loop_const_init(ctx, 0);
unsigned i;
/* The number of dwords all the dirty states would take. */
- for (i = 0; i < R600_MAX_ATOM; i++) {
+ for (i = 0; i < R600_NUM_ATOMS; i++) {
if (ctx->atoms[i] && ctx->atoms[i]->dirty) {
num_dw += ctx->atoms[i]->num_dw;
}
num_dw += ctx->pm4_dirty_cdwords;
- /* The upper-bound of how much a draw command would take. */
- num_dw += R600_MAX_DRAW_CS_DWORDS;
+ /* The upper-bound of how much space a draw command would take. */
+ num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
}
/* Count in queries_suspend. */
num_dw += 3;
}
+ /* SX_MISC */
+ if (ctx->chip_class <= R700) {
+ num_dw += 3;
+ }
+
/* Count in framebuffer cache flushes at the end of CS. */
- num_dw += 44; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */
+ num_dw += R600_MAX_FLUSH_CS_DWORDS;
- /* Save 16 dwords for the fence mechanism. */
- num_dw += 16;
+ /* The fence at the end of CS. */
+ num_dw += 10;
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
void r600_context_flush(struct r600_context *ctx, unsigned flags)
{
struct radeon_winsys_cs *cs = ctx->cs;
- struct r600_block *enable_block = NULL;
- bool timer_queries_suspended = false;
- bool nontimer_queries_suspended = false;
- bool streamout_suspended = false;
- unsigned shader;
if (cs->cdw == ctx->start_cs_cmd.atom.num_dw)
return;
+ ctx->timer_queries_suspended = false;
+ ctx->nontimer_queries_suspended = false;
+ ctx->streamout_suspended = false;
+
/* suspend queries */
if (ctx->num_cs_dw_timer_queries_suspend) {
r600_suspend_timer_queries(ctx);
- timer_queries_suspended = true;
+ ctx->timer_queries_suspended = true;
}
if (ctx->num_cs_dw_nontimer_queries_suspend) {
r600_suspend_nontimer_queries(ctx);
- nontimer_queries_suspended = true;
+ ctx->nontimer_queries_suspended = true;
}
if (ctx->num_cs_dw_streamout_end) {
r600_context_streamout_end(ctx);
- streamout_suspended = true;
+ ctx->streamout_suspended = true;
}
/* partial flush is needed to avoid lockups on some chips with user fences */
/* Flush the CS. */
ctx->ws->cs_flush(ctx->cs, flags);
+ r600_begin_new_cs(ctx);
+}
+
+void r600_begin_new_cs(struct r600_context *ctx)
+{
+ struct r600_block *enable_block = NULL;
+ unsigned shader;
+
ctx->pm4_dirty_cdwords = 0;
ctx->flags = 0;
/* Re-emit states. */
r600_atom_dirty(ctx, &ctx->alphatest_state.atom);
+ r600_atom_dirty(ctx, &ctx->blend_color.atom);
r600_atom_dirty(ctx, &ctx->cb_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->clip_state.atom);
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
+ r600_atom_dirty(ctx, &ctx->vgt_state.atom);
+ r600_atom_dirty(ctx, &ctx->vgt2_state.atom);
+ r600_atom_dirty(ctx, &ctx->sample_mask.atom);
+ r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
+ r600_atom_dirty(ctx, &ctx->viewport.atom);
if (ctx->chip_class <= R700) {
r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);
}
- r600_atom_dirty(ctx, &ctx->sample_mask.atom);
ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
r600_vertex_buffers_dirty(ctx);
r600_sampler_states_dirty(ctx, &samplers->states);
}
- if (streamout_suspended) {
+ if (ctx->streamout_suspended) {
ctx->streamout_start = TRUE;
ctx->streamout_append_bitmask = ~0;
}
/* resume queries */
- if (timer_queries_suspended) {
+ if (ctx->timer_queries_suspended) {
r600_resume_timer_queries(ctx);
}
- if (nontimer_queries_suspended) {
+ if (ctx->nontimer_queries_suspended) {
r600_resume_nontimer_queries(ctx);
}
ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords;
enable_block->nreg_dirty = enable_block->nreg;
}
+
+ /* Re-emit the draw state. */
+ ctx->last_primitive_type = -1;
+ ctx->last_start_instance = -1;
}
void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value)
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