#include "r600_pipe.h"
#include "radeon_llvm.h"
#include "radeon_llvm_emit.h"
+#include "radeon_elf_util.h"
#include <stdio.h>
#define CONSTANT_BUFFER_0_ADDR_SPACE 8
#define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + R600_UCP_CONST_BUFFER)
-#define CONSTANT_TXQ_BUFFER (CONSTANT_BUFFER_0_ADDR_SPACE + R600_TXQ_CONST_BUFFER)
#define LLVM_R600_BUFFER_INFO_CONST_BUFFER \
(CONSTANT_BUFFER_0_ADDR_SPACE + R600_BUFFER_INFO_CONST_BUFFER)
default: assert(!"unknown system value");
}
+#if HAVE_LLVM >= 0x0304
+ ctx->system_values[index] = LLVMBuildExtractElement(ctx->gallivm.builder,
+ LLVMGetParam(ctx->main_fn, 0), lp_build_const_int32(&(ctx->gallivm), chan),
+ "");
+#else
LLVMValueRef reg = lp_build_const_int32(
ctx->soa.bld_base.base.gallivm, chan);
ctx->system_values[index] = build_intrinsic(
"llvm.R600.load.input",
ctx->soa.bld_base.base.elem_type, ®, 1,
LLVMReadNoneAttribute);
+#endif
}
+#if HAVE_LLVM >= 0x0304
+static LLVMValueRef
+llvm_load_input_vector(
+ struct radeon_llvm_context * ctx, unsigned location, unsigned ijregs,
+ boolean interp)
+{
+ LLVMTypeRef VecType;
+ LLVMValueRef Args[3] = {
+ lp_build_const_int32(&(ctx->gallivm), location)
+ };
+ unsigned ArgCount = 1;
+ if (interp) {
+ VecType = LLVMVectorType(ctx->soa.bld_base.base.elem_type, 2);
+ LLVMValueRef IJIndex = LLVMGetParam(ctx->main_fn, ijregs / 2);
+ Args[ArgCount++] = LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex,
+ lp_build_const_int32(&(ctx->gallivm), 2 * (ijregs % 2)), "");
+ Args[ArgCount++] = LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex,
+ lp_build_const_int32(&(ctx->gallivm), 2 * (ijregs % 2) + 1), "");
+ LLVMValueRef HalfVec[2] = {
+ build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.xy",
+ VecType, Args, ArgCount, LLVMReadNoneAttribute),
+ build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.zw",
+ VecType, Args, ArgCount, LLVMReadNoneAttribute)
+ };
+ LLVMValueRef MaskInputs[4] = {
+ lp_build_const_int32(&(ctx->gallivm), 0),
+ lp_build_const_int32(&(ctx->gallivm), 1),
+ lp_build_const_int32(&(ctx->gallivm), 2),
+ lp_build_const_int32(&(ctx->gallivm), 3)
+ };
+ LLVMValueRef Mask = LLVMConstVector(MaskInputs, 4);
+ return LLVMBuildShuffleVector(ctx->gallivm.builder, HalfVec[0], HalfVec[1],
+ Mask, "");
+ } else {
+ VecType = LLVMVectorType(ctx->soa.bld_base.base.elem_type, 4);
+ return build_intrinsic(ctx->gallivm.builder, "llvm.R600.interp.const",
+ VecType, Args, ArgCount, LLVMReadNoneAttribute);
+ }
+}
+#else
static LLVMValueRef
llvm_load_input_helper(
struct radeon_llvm_context * ctx,
return build_intrinsic(bb->gallivm->builder, intrinsic,
bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
}
+#endif
+#if HAVE_LLVM >= 0x0304
+static LLVMValueRef
+llvm_face_select_helper(
+ struct radeon_llvm_context * ctx,
+ LLVMValueRef face, LLVMValueRef front_color, LLVMValueRef back_color)
+{
+ const struct lp_build_context * bb = &ctx->soa.bld_base.base;
+ LLVMValueRef is_front = LLVMBuildFCmp(
+ bb->gallivm->builder, LLVMRealUGT, face,
+ lp_build_const_float(bb->gallivm, 0.0f), "");
+ return LLVMBuildSelect(bb->gallivm->builder, is_front,
+ front_color, back_color, "");
+}
+#else
static LLVMValueRef
llvm_face_select_helper(
struct radeon_llvm_context * ctx,
return LLVMBuildSelect(bb->gallivm->builder, is_front,
front_color, back_color, "");
}
+#endif
static void llvm_load_input(
struct radeon_llvm_context * ctx,
{
const struct r600_shader_io * input = &ctx->r600_inputs[input_index];
unsigned chan;
+#if HAVE_LLVM < 0x0304
unsigned interp = 0;
int ij_index;
+#endif
int two_side = (ctx->two_side && input->name == TGSI_SEMANTIC_COLOR);
LLVMValueRef v;
+#if HAVE_LLVM >= 0x0304
+ boolean require_interp_intrinsic = ctx->chip_class >= EVERGREEN &&
+ ctx->type == TGSI_PROCESSOR_FRAGMENT;
+#endif
+
+#if HAVE_LLVM >= 0x0304
+ if (require_interp_intrinsic && input->spi_sid) {
+ v = llvm_load_input_vector(ctx, input->lds_pos, input->ij_index,
+ (input->interpolate > 0));
+ } else
+ v = LLVMGetParam(ctx->main_fn, input->gpr);
+
+ if (two_side) {
+ struct r600_shader_io * back_input =
+ &ctx->r600_inputs[input->back_color_input];
+ LLVMValueRef v2;
+ LLVMValueRef face = LLVMGetParam(ctx->main_fn, ctx->face_gpr);
+ face = LLVMBuildExtractElement(ctx->gallivm.builder, face,
+ lp_build_const_int32(&(ctx->gallivm), 0), "");
+
+ if (require_interp_intrinsic && back_input->spi_sid)
+ v2 = llvm_load_input_vector(ctx, back_input->lds_pos,
+ back_input->ij_index, (back_input->interpolate > 0));
+ else
+ v2 = LLVMGetParam(ctx->main_fn, back_input->gpr);
+ v = llvm_face_select_helper(ctx, face, v, v2);
+ }
+ for (chan = 0; chan < 4; chan++) {
+ unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
+
+ ctx->inputs[soa_index] = LLVMBuildExtractElement(ctx->gallivm.builder, v,
+ lp_build_const_int32(&(ctx->gallivm), chan), "");
+
+ if (input->name == TGSI_SEMANTIC_POSITION &&
+ ctx->type == TGSI_PROCESSOR_FRAGMENT && chan == 3) {
+ /* RCP for fragcoord.w */
+ ctx->inputs[soa_index] = LLVMBuildFDiv(ctx->gallivm.builder,
+ lp_build_const_float(&(ctx->gallivm), 1.0f),
+ ctx->inputs[soa_index], "");
+ }
+}
+#else
if (ctx->chip_class >= EVERGREEN && ctx->type == TGSI_PROCESSOR_FRAGMENT &&
input->spi_sid) {
interp = 1;
ctx->inputs[soa_index] = v;
}
+#endif
}
static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
case TGSI_SEMANTIC_CLIPVERTEX: {
LLVMValueRef args[3];
unsigned reg_index;
- unsigned base_vector_chan;
LLVMValueRef adjusted_elements[4];
for (reg_index = 0; reg_index < 2; reg_index ++) {
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
case TGSI_OPCODE_TXQ: {
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
ctx->uses_tex_buffers = true;
- LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, 0);
+ bool isEgPlus = (ctx->chip_class >= EVERGREEN);
+ LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm,
+ isEgPlus ? 0 : 1);
LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, offset,
LLVM_R600_BUFFER_INFO_CONST_BUFFER);
+ if (!isEgPlus) {
+ LLVMValueRef maskval[4] = {
+ lp_build_const_int32(gallivm, 1),
+ lp_build_const_int32(gallivm, 2),
+ lp_build_const_int32(gallivm, 3),
+ lp_build_const_int32(gallivm, 0),
+ };
+ LLVMValueRef mask = LLVMConstVector(maskval, 4);
+ cvecval = LLVMBuildShuffleVector(gallivm->builder, cvecval, cvecval,
+ mask, "");
+ }
emit_data->output[0] = cvecval;
return;
}
emit_data->output[0] = build_intrinsic(gallivm->builder,
"llvm.R600.load.texbuf",
emit_data->dst_type, args, 2, LLVMReadNoneAttribute);
+ if (ctx->chip_class >= EVERGREEN)
+ return;
+ ctx->uses_tex_buffers = true;
+ LLVMDumpValue(emit_data->output[0]);
+ emit_data->output[0] = LLVMBuildBitCast(gallivm->builder,
+ emit_data->output[0], LLVMVectorType(bld_base->base.int_elem_type, 4),
+ "");
+ LLVMValueRef Mask = llvm_load_const_buffer(bld_base,
+ lp_build_const_int32(gallivm, 0),
+ LLVM_R600_BUFFER_INFO_CONST_BUFFER);
+ Mask = LLVMBuildBitCast(gallivm->builder, Mask,
+ LLVMVectorType(bld_base->base.int_elem_type, 4), "");
+ emit_data->output[0] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_AND,
+ emit_data->output[0],
+ Mask);
+ LLVMValueRef WComponent = LLVMBuildExtractElement(gallivm->builder,
+ emit_data->output[0], lp_build_const_int32(gallivm, 3), "");
+ Mask = llvm_load_const_buffer(bld_base, lp_build_const_int32(gallivm, 1),
+ LLVM_R600_BUFFER_INFO_CONST_BUFFER);
+ Mask = LLVMBuildExtractElement(gallivm->builder, Mask,
+ lp_build_const_int32(gallivm, 0), "");
+ Mask = LLVMBuildBitCast(gallivm->builder, Mask,
+ bld_base->base.int_elem_type, "");
+ WComponent = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_OR,
+ WComponent, Mask);
+ emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder,
+ emit_data->output[0], WComponent, lp_build_const_int32(gallivm, 3), "");
+ emit_data->output[0] = LLVMBuildBitCast(gallivm->builder,
+ emit_data->output[0], LLVMVectorType(bld_base->base.elem_type, 4), "");
}
return;
default:
if (emit_data->inst->Dst[0].Register.WriteMask & 4) {
LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, 0);
LLVMValueRef ZLayer = LLVMBuildExtractElement(gallivm->builder,
- llvm_load_const_buffer(bld_base, offset, CONSTANT_TXQ_BUFFER),
+ llvm_load_const_buffer(bld_base, offset, LLVM_R600_BUFFER_INFO_CONST_BUFFER),
lp_build_const_int32(gallivm, 0), "");
emit_data->output[0] = LLVMBuildInsertElement(gallivm->builder, emit_data->output[0], ZLayer, lp_build_const_int32(gallivm, 2), "");
struct tgsi_shader_info shader_info;
struct lp_build_tgsi_context * bld_base = &ctx->soa.bld_base;
radeon_llvm_context_init(ctx);
+#if HAVE_LLVM >= 0x0304
+ LLVMTypeRef Arguments[32];
+ unsigned ArgumentsCount = 0;
+ for (unsigned i = 0; i < ctx->inputs_count; i++)
+ Arguments[ArgumentsCount++] = LLVMVectorType(bld_base->base.elem_type, 4);
+ radeon_llvm_create_func(ctx, Arguments, ArgumentsCount);
+ for (unsigned i = 0; i < ctx->inputs_count; i++) {
+ LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
+ LLVMAddAttribute(P, LLVMInRegAttribute);
+ }
+#else
radeon_llvm_create_func(ctx, NULL, 0);
+#endif
tgsi_scan_shader(tokens, &shader_info);
bld_base->info = &shader_info;
#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
#define R_028850_SQ_PGM_RESOURCES_PS 0x028850
-unsigned r600_llvm_compile(
- LLVMModuleRef mod,
- enum radeon_family family,
- struct r600_bytecode *bc,
- boolean *use_kill,
- unsigned dump)
+void r600_shader_binary_read_config(const struct radeon_shader_binary *binary,
+ struct r600_bytecode *bc,
+ uint64_t symbol_offset,
+ boolean *use_kill)
{
- unsigned r;
- struct radeon_llvm_binary binary;
- const char * gpu_family = r600_llvm_gpu_string(family);
unsigned i;
+ const unsigned char *config =
+ radeon_shader_binary_config_start(binary, symbol_offset);
- r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
-
- assert(binary.code_size % 4 == 0);
- bc->bytecode = CALLOC(1, binary.code_size);
- memcpy(bc->bytecode, binary.code, binary.code_size);
- bc->ndw = binary.code_size / 4;
-
- for (i = 0; i < binary.config_size; i+= 8) {
+ for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
unsigned reg =
- util_le32_to_cpu(*(uint32_t*)(binary.config + i));
+ util_le32_to_cpu(*(uint32_t*)(config + i));
unsigned value =
- util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
+ util_le32_to_cpu(*(uint32_t*)(config + i + 4));
switch (reg) {
/* R600 / R700 */
case R_028850_SQ_PGM_RESOURCES_PS:
case R_028844_SQ_PGM_RESOURCES_PS:
case R_028860_SQ_PGM_RESOURCES_VS:
case R_0288D4_SQ_PGM_RESOURCES_LS:
- bc->ngpr = G_028844_NUM_GPRS(value);
- bc->nstack = G_028844_STACK_SIZE(value);
+ bc->ngpr = MAX2(bc->ngpr, G_028844_NUM_GPRS(value));
+ bc->nstack = MAX2(bc->nstack, G_028844_STACK_SIZE(value));
break;
case R_02880C_DB_SHADER_CONTROL:
*use_kill = G_02880C_KILL_ENABLE(value);
}
}
+}
+
+unsigned r600_create_shader(struct r600_bytecode *bc,
+ const struct radeon_shader_binary *binary,
+ boolean *use_kill)
+
+{
+ assert(binary->code_size % 4 == 0);
+ bc->bytecode = CALLOC(1, binary->code_size);
+ memcpy(bc->bytecode, binary->code, binary->code_size);
+ bc->ndw = binary->code_size / 4;
+
+ r600_shader_binary_read_config(binary, bc, 0, use_kill);
+
+ return 0;
+}
+
+unsigned r600_llvm_compile(
+ LLVMModuleRef mod,
+ enum radeon_family family,
+ struct r600_bytecode *bc,
+ boolean *use_kill,
+ unsigned dump)
+{
+ unsigned r;
+ struct radeon_shader_binary binary;
+ const char * gpu_family = r600_get_llvm_processor_name(family);
+
+ memset(&binary, 0, sizeof(struct radeon_shader_binary));
+ r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
+
+ r = r600_create_shader(bc, &binary, use_kill);
+
+ FREE(binary.code);
+ FREE(binary.config);
+ FREE(binary.rodata);
+ FREE(binary.global_symbol_offsets);
+
return r;
}
projects / mesa.git / blobdiff