#include "gallivm/lp_bld_gather.h"
#include "tgsi/tgsi_parse.h"
#include "util/u_double_list.h"
+#include "util/u_memory.h"
#include "r600.h"
#include "r600_asm.h"
#include <stdio.h>
+#if defined R600_USE_LLVM || defined HAVE_OPENCL
+
static LLVMValueRef llvm_fetch_const(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type,
unsigned swizzle)
{
- LLVMValueRef cval = lp_build_intrinsic_unary(bld_base->base.gallivm->builder,
+ LLVMValueRef idx = lp_build_const_int32(bld_base->base.gallivm,
+ radeon_llvm_reg_index_soa(reg->Register.Index, swizzle));
+ LLVMValueRef cval = build_intrinsic(bld_base->base.gallivm->builder,
"llvm.AMDGPU.load.const", bld_base->base.elem_type,
- lp_build_const_int32(bld_base->base.gallivm,
- radeon_llvm_reg_index_soa(reg->Register.Index, swizzle)));
+ &idx, 1, LLVMReadNoneAttribute);
return bitcast(bld_base, type, cval);
}
LLVMValueRef reg = lp_build_const_int32(
ctx->soa.bld_base.base.gallivm, chan);
- ctx->system_values[index] = lp_build_intrinsic_unary(
+ ctx->system_values[index] = build_intrinsic(
ctx->soa.bld_base.base.gallivm->builder,
"llvm.R600.load.input",
- ctx->soa.bld_base.base.elem_type, reg);
+ ctx->soa.bld_base.base.elem_type, ®, 1,
+ LLVMReadNoneAttribute);
}
static LLVMValueRef llvm_fetch_system_value(
LLVMValueRef reg = lp_build_const_int32(
ctx->soa.bld_base.base.gallivm,
soa_index + (ctx->reserved_reg_count * 4));
- ctx->inputs[soa_index] = lp_build_intrinsic_unary(
+ ctx->inputs[soa_index] = build_intrinsic(
ctx->soa.bld_base.base.gallivm->builder,
"llvm.R600.load.input",
- ctx->soa.bld_base.base.elem_type, reg);
+ ctx->soa.bld_base.base.elem_type, ®, 1,
+ LLVMReadNoneAttribute);
}
}
struct lp_build_emit_data * emit_data)
{
struct gallivm_state * gallivm = bld_base->base.gallivm;
- LLVMValueRef args[3];
+ LLVMValueRef args[6];
+ unsigned c, sampler_src;
+
+ assert(emit_data->arg_count + 2 <= Elements(args));
+
+ for (c = 0; c < emit_data->arg_count; ++c)
+ args[c] = emit_data->args[c];
- args[0] = emit_data->args[0];
- args[1] = lp_build_const_int32(gallivm,
- emit_data->inst->Src[1].Register.Index);
- args[2] = lp_build_const_int32(gallivm,
+ sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
+
+ args[c++] = lp_build_const_int32(gallivm,
+ emit_data->inst->Src[sampler_src].Register.Index);
+ args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Texture.Texture);
- emit_data->output[0] = lp_build_intrinsic(gallivm->builder,
+
+ emit_data->output[0] = build_intrinsic(gallivm->builder,
action->intr_name,
- emit_data->dst_type, args, 3);
+ emit_data->dst_type, args, c, LLVMReadNoneAttribute);
}
static void dp_fetch_args(
static struct lp_build_tgsi_action dot_action = {
.fetch_args = dp_fetch_args,
- .emit = lp_build_tgsi_intrinsic,
+ .emit = build_tgsi_intrinsic_nomem,
.intr_name = "llvm.AMDGPU.dp4"
};
return radeon_llvm_compile(mod, inst_bytes, inst_byte_count,
gpu_family, dump);
}
+
+#endif