vc4: Add support for 16-bit signed/unsigned norm/scaled vertex attrs.

[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 73c6e3543afdca8246073ab3831bc4a0e72b294e..0b571e45e9b711baef5dd73558d58db8612f3740 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -191,6 +191,9 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
        if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
                goto fail;
 
+       if (rscreen->b.debug_flags & DBG_FORCE_DMA)
+               rctx->b.b.resource_copy_region = rctx->b.dma_copy;
+
        rctx->blitter = util_blitter_create(&rctx->b.b);
        if (rctx->blitter == NULL)
                goto fail;
@@ -262,6 +265,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
        case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
        case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+       case PIPE_CAP_SAMPLE_SHADING:
+       case PIPE_CAP_CLIP_HALFZ:
                return 1;
 
        case PIPE_CAP_COMPUTE:
@@ -316,7 +321,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
        case PIPE_CAP_VERTEX_COLOR_CLAMPED:
        case PIPE_CAP_USER_VERTEX_BUFFERS:
-       case PIPE_CAP_SAMPLE_SHADING:
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
        case PIPE_CAP_DRAW_INDIRECT:
        case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
@@ -431,6 +435,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 32;
        case PIPE_SHADER_CAP_MAX_INPUTS:
                return shader == PIPE_SHADER_VERTEX ? 16 : 32;
+       case PIPE_SHADER_CAP_MAX_OUTPUTS:
+               return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
        case PIPE_SHADER_CAP_MAX_TEMPS:
                return 256; /* Max native temporaries. */
        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
@@ -466,7 +472,11 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 16;
         case PIPE_SHADER_CAP_PREFERRED_IR:
                if (shader == PIPE_SHADER_COMPUTE) {
+#if HAVE_LLVM < 0x0306
                        return PIPE_SHADER_IR_LLVM;
+#else
+                       return PIPE_SHADER_IR_NATIVE;
+#endif
                } else {
                        return PIPE_SHADER_IR_TGSI;
                }
@@ -534,8 +544,8 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
                rscreen->b.debug_flags |= DBG_COMPUTE;
        if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
                rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
-       if (debug_get_bool_option("R600_HYPERZ", FALSE))
-               rscreen->b.debug_flags |= DBG_HYPERZ;
+       if (!debug_get_bool_option("R600_HYPERZ", TRUE))
+               rscreen->b.debug_flags |= DBG_NO_HYPERZ;
        if (debug_get_bool_option("R600_LLVM", FALSE))
                rscreen->b.debug_flags |= DBG_LLVM;