vc4: Add support for 16-bit signed/unsigned norm/scaled vertex attrs.

[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 8a5ba7951bbd487103e32b65bb9431680a5d3c75..0b571e45e9b711baef5dd73558d58db8612f3740 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -30,7 +30,6 @@
 
 #include <errno.h>
 #include "pipe/p_shader_tokens.h"
-#include "util/u_blitter.h"
 #include "util/u_debug.h"
 #include "util/u_memory.h"
 #include "util/u_simple_shaders.h"
@@ -192,6 +191,9 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
        if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
                goto fail;
 
+       if (rscreen->b.debug_flags & DBG_FORCE_DMA)
+               rctx->b.b.resource_copy_region = rctx->b.dma_copy;
+
        rctx->blitter = util_blitter_create(&rctx->b.b);
        if (rctx->blitter == NULL)
                goto fail;
@@ -262,6 +264,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
        case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
+       case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+       case PIPE_CAP_SAMPLE_SHADING:
+       case PIPE_CAP_CLIP_HALFZ:
                return 1;
 
        case PIPE_CAP_COMPUTE:
@@ -302,9 +307,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        /* Supported on Evergreen. */
        case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
        case PIPE_CAP_CUBE_MAP_ARRAY:
-       case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
        case PIPE_CAP_TEXTURE_GATHER_SM5:
        case PIPE_CAP_TEXTURE_QUERY_LOD:
+       case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
                return family >= CHIP_CEDAR ? 1 : 0;
        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
                return family >= CHIP_CEDAR ? 4 : 0;
@@ -316,10 +321,10 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
        case PIPE_CAP_VERTEX_COLOR_CLAMPED:
        case PIPE_CAP_USER_VERTEX_BUFFERS:
-       case PIPE_CAP_SAMPLE_SHADING:
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
        case PIPE_CAP_DRAW_INDIRECT:
-       case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
+       case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
+       case PIPE_CAP_SAMPLER_VIEW_TARGET:
                return 0;
 
        /* Stream output. */
@@ -339,6 +344,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_VERTEX_STREAMS:
                return 1;
 
+       case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
+               return 2047;
+
        /* Texturing. */
        case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
@@ -380,6 +388,17 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
        case PIPE_CAP_ENDIANNESS:
                return PIPE_ENDIAN_LITTLE;
+
+       case PIPE_CAP_VENDOR_ID:
+               return 0x1002;
+       case PIPE_CAP_DEVICE_ID:
+               return rscreen->b.info.pci_id;
+       case PIPE_CAP_ACCELERATED:
+               return 1;
+       case PIPE_CAP_VIDEO_MEMORY:
+               return rscreen->b.info.vram_size >> 20;
+       case PIPE_CAP_UMA:
+               return 0;
        }
        return 0;
 }
@@ -416,6 +435,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 32;
        case PIPE_SHADER_CAP_MAX_INPUTS:
                return shader == PIPE_SHADER_VERTEX ? 16 : 32;
+       case PIPE_SHADER_CAP_MAX_OUTPUTS:
+               return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
        case PIPE_SHADER_CAP_MAX_TEMPS:
                return 256; /* Max native temporaries. */
        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
@@ -451,7 +472,11 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 16;
         case PIPE_SHADER_CAP_PREFERRED_IR:
                if (shader == PIPE_SHADER_COMPUTE) {
+#if HAVE_LLVM < 0x0306
                        return PIPE_SHADER_IR_LLVM;
+#else
+                       return PIPE_SHADER_IR_NATIVE;
+#endif
                } else {
                        return PIPE_SHADER_IR_TGSI;
                }
@@ -519,8 +544,8 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
                rscreen->b.debug_flags |= DBG_COMPUTE;
        if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
                rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
-       if (debug_get_bool_option("R600_HYPERZ", FALSE))
-               rscreen->b.debug_flags |= DBG_HYPERZ;
+       if (!debug_get_bool_option("R600_HYPERZ", TRUE))
+               rscreen->b.debug_flags |= DBG_NO_HYPERZ;
        if (debug_get_bool_option("R600_LLVM", FALSE))
                rscreen->b.debug_flags |= DBG_LLVM;