gallium/radeon: inline the r600_rings structure
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
index 566e724d02bf58a0d59265c31182b637bd5302d2..bd00dcb642c53045e504f29eeba376c5e8b3bbe8 100644 (file)
@@ -108,7 +108,8 @@ static void r600_destroy_context(struct pipe_context *context)
        FREE(rctx);
 }
 
-static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
+static struct pipe_context *r600_create_context(struct pipe_screen *screen,
+                                                void *priv, unsigned flags)
 {
        struct r600_context *rctx = CALLOC_STRUCT(r600_context);
        struct r600_screen* rscreen = (struct r600_screen *)screen;
@@ -120,6 +121,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
        rctx->b.b.screen = screen;
        rctx->b.b.priv = priv;
        rctx->b.b.destroy = r600_destroy_context;
+       rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 
        if (!r600_common_context_init(&rctx->b, &rscreen->b))
                goto fail;
@@ -176,11 +178,11 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
                goto fail;
        }
 
-       rctx->b.rings.gfx.cs = ws->cs_create(ws, RING_GFX,
-                                            r600_context_gfx_flush, rctx,
-                                            rscreen->b.trace_bo ?
-                                                    rscreen->b.trace_bo->cs_buf : NULL);
-       rctx->b.rings.gfx.flush = r600_context_gfx_flush;
+       rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
+                                      r600_context_gfx_flush, rctx,
+                                      rscreen->b.trace_bo ?
+                                              rscreen->b.trace_bo->cs_buf : NULL);
+       rctx->b.gfx.flush = r600_context_gfx_flush;
 
        rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
                                                             0, PIPE_USAGE_DEFAULT, FALSE);
@@ -191,6 +193,9 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
        if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
                goto fail;
 
+       if (rscreen->b.debug_flags & DBG_FORCE_DMA)
+               rctx->b.b.resource_copy_region = rctx->b.dma_copy;
+
        rctx->blitter = util_blitter_create(&rctx->b.b);
        if (rctx->blitter == NULL)
                goto fail;
@@ -261,8 +266,22 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
        case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
+       case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+       case PIPE_CAP_SAMPLE_SHADING:
+       case PIPE_CAP_CLIP_HALFZ:
+       case PIPE_CAP_POLYGON_OFFSET_CLAMP:
+       case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
+       case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
+       case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
+       case PIPE_CAP_TGSI_TXQS:
                return 1;
 
+       case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
+               return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
+
+       case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
+               return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
+
        case PIPE_CAP_COMPUTE:
                return rscreen->b.chip_class > R700;
 
@@ -286,7 +305,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
                if (family >= CHIP_CEDAR)
-                  return 330;
+                  return 410;
                /* pre-evergreen geom shaders need newer kernel */
                if (rscreen->b.info.drm_minor >= 37)
                   return 330;
@@ -301,13 +320,16 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        /* Supported on Evergreen. */
        case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
        case PIPE_CAP_CUBE_MAP_ARRAY:
-       case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
        case PIPE_CAP_TEXTURE_GATHER_SM5:
        case PIPE_CAP_TEXTURE_QUERY_LOD:
        case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
+       case PIPE_CAP_SAMPLER_VIEW_TARGET:
                return family >= CHIP_CEDAR ? 1 : 0;
        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
                return family >= CHIP_CEDAR ? 4 : 0;
+       case PIPE_CAP_DRAW_INDIRECT:
+               /* kernel command checker support is also required */
+               return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 
        /* Unsupported features. */
        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -316,10 +338,14 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
        case PIPE_CAP_VERTEX_COLOR_CLAMPED:
        case PIPE_CAP_USER_VERTEX_BUFFERS:
-       case PIPE_CAP_SAMPLE_SHADING:
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
-       case PIPE_CAP_DRAW_INDIRECT:
-       case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
+       case PIPE_CAP_VERTEXID_NOBASE:
+       case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+       case PIPE_CAP_DEPTH_BOUNDS_TEST:
+       case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+       case PIPE_CAP_SHAREABLE_SHADERS:
+       case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
+       case PIPE_CAP_CLEAR_TEXTURE:
                return 0;
 
        /* Stream output. */
@@ -337,7 +363,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
                return 16384;
        case PIPE_CAP_MAX_VERTEX_STREAMS:
-               return 1;
+               return family >= CHIP_CEDAR ? 4 : 1;
 
        case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
                return 2047;
@@ -362,7 +388,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 8;
 
        case PIPE_CAP_MAX_VIEWPORTS:
-               return 16;
+               return R600_MAX_VIEWPORTS;
 
        /* Timer queries, present when the clock frequency is non zero. */
        case PIPE_CAP_QUERY_TIME_ELAPSED:
@@ -394,6 +420,8 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return rscreen->b.info.vram_size >> 20;
        case PIPE_CAP_UMA:
                return 0;
+       case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
+               return rscreen->b.chip_class >= R700;
        }
        return 0;
 }
@@ -430,6 +458,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 32;
        case PIPE_SHADER_CAP_MAX_INPUTS:
                return shader == PIPE_SHADER_VERTEX ? 16 : 32;
+       case PIPE_SHADER_CAP_MAX_OUTPUTS:
+               return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
        case PIPE_SHADER_CAP_MAX_TEMPS:
                return 256; /* Max native temporaries. */
        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
@@ -459,18 +489,36 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
        case PIPE_SHADER_CAP_SUBROUTINES:
                return 0;
        case PIPE_SHADER_CAP_INTEGERS:
+       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
                return 1;
        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
                return 16;
         case PIPE_SHADER_CAP_PREFERRED_IR:
                if (shader == PIPE_SHADER_COMPUTE) {
+#if HAVE_LLVM < 0x0306
                        return PIPE_SHADER_IR_LLVM;
+#else
+                       return PIPE_SHADER_IR_NATIVE;
+#endif
                } else {
                        return PIPE_SHADER_IR_TGSI;
                }
        case PIPE_SHADER_CAP_DOUBLES:
+               if (rscreen->b.family == CHIP_CYPRESS ||
+                       rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
+                       return 1;
+               return 0;
+       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
+       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
                return 0;
+       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
+               /* due to a bug in the shader compiler, some loops hang
+                * if they are not unrolled, see:
+                *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
+                */
+               return 255;
        }
        return 0;
 }
@@ -533,8 +581,8 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
                rscreen->b.debug_flags |= DBG_COMPUTE;
        if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
                rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
-       if (debug_get_bool_option("R600_HYPERZ", FALSE))
-               rscreen->b.debug_flags |= DBG_HYPERZ;
+       if (!debug_get_bool_option("R600_HYPERZ", TRUE))
+               rscreen->b.debug_flags |= DBG_NO_HYPERZ;
        if (debug_get_bool_option("R600_LLVM", FALSE))
                rscreen->b.debug_flags |= DBG_LLVM;
 
@@ -591,7 +639,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        rscreen->global_pool = compute_memory_pool_new(rscreen);
 
        /* Create the auxiliary context. This must be done last. */
-       rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
+       rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 
 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
        struct pipe_resource templ = {};