if (rctx->custom_dsa_flush) {
rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
}
+ if (rctx->custom_blend_resolve) {
+ rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve);
+ }
util_unreference_framebuffer_state(&rctx->framebuffer);
r600_context_fini(rctx);
if (evergreen_context_init(rctx))
goto fail;
rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
+ rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR ||
rctx->family == CHIP_PALM ||
rctx->family == CHIP_SUMO ||
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_USER_VERTEX_BUFFERS:
- case PIPE_CAP_QUERY_TIMESTAMP:
return 0;
/* Stream output. */
/* Timer queries, present when the clock frequency is non zero. */
case PIPE_CAP_TIMER_QUERY:
return rscreen->info.r600_clock_crystal_freq != 0;
+ case PIPE_CAP_QUERY_TIMESTAMP:
+ return rscreen->info.drm_minor >= 20 &&
+ rscreen->info.r600_clock_crystal_freq != 0;
case PIPE_CAP_MIN_TEXEL_OFFSET:
return -8;
}
}
+static uint64_t r600_get_timestamp(struct pipe_screen *screen)
+{
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
+
+ return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) /
+ rscreen->info.r600_clock_crystal_freq;
+}
+
struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
{
struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
rscreen->screen.get_paramf = r600_get_paramf;
rscreen->screen.get_video_param = r600_get_video_param;
rscreen->screen.get_compute_param = r600_get_compute_param;
+ rscreen->screen.get_timestamp = r600_get_timestamp;
if (rscreen->chip_class >= EVERGREEN) {
rscreen->screen.is_format_supported = evergreen_is_format_supported;