freedreno/ir3: fix half-reg array stores
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
index 3ffead9eb29edf56c3cf28b37913a0913d8b03d7..d65b2841613d2d986077b87ed1b110c9f8b4417c 100644 (file)
@@ -288,6 +288,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_VERTEX_SHADER_SATURATE:
        case PIPE_CAP_SEAMLESS_CUBE_MAP:
        case PIPE_CAP_PRIMITIVE_RESTART:
+       case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
        case PIPE_CAP_CONDITIONAL_RENDER:
        case PIPE_CAP_TEXTURE_BARRIER:
        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
@@ -339,8 +340,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return rscreen->b.chip_class > R700;
 
        case PIPE_CAP_TGSI_TEXCOORD:
-               return is_nir_enabled(&rscreen->b);
+               return 1;
 
+       case PIPE_CAP_NIR_IMAGES_AS_DEREF:
        case PIPE_CAP_FAKE_SW_MSAA:
                return 0;
 
@@ -561,9 +563,11 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_TESS_EVAL:
                if (rscreen->b.family >= CHIP_CEDAR)
                        break;
+               /* fallthrough */
        case PIPE_SHADER_COMPUTE:
                if (!is_nir_enabled(&rscreen->b))
                        break;
+               /* fallthrough */
        default:
                return 0;
        }
@@ -609,6 +613,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_SUBROUTINES:
        case PIPE_SHADER_CAP_INT64_ATOMICS:
        case PIPE_SHADER_CAP_FP16:
+        case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+        case PIPE_SHADER_CAP_INT16:
+        case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
                return 0;
        case PIPE_SHADER_CAP_INTEGERS:
        case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: