swr: fix build with mingw

[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 831d348b43093bfe7f2dc9e0f02fff2d571fafe9..eb26074221a635fb239b66347e5a792b02d88ea4 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -249,6 +249,12 @@ fail:
        return NULL;
 }
 
+static bool is_nir_enabled(struct r600_common_screen *screen) {
+   return (screen->debug_flags & DBG_NIR &&
+       screen->family >= CHIP_CEDAR &&
+       screen->family < CHIP_CAYMAN);
+}
+
 /*
  * pipe_screen
  */
@@ -282,6 +288,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_VERTEX_SHADER_SATURATE:
        case PIPE_CAP_SEAMLESS_CUBE_MAP:
        case PIPE_CAP_PRIMITIVE_RESTART:
+       case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
        case PIPE_CAP_CONDITIONAL_RENDER:
        case PIPE_CAP_TEXTURE_BARRIER:
        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
@@ -317,6 +324,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
        case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+        case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
                return 1;
 
        case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
@@ -333,8 +341,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return rscreen->b.chip_class > R700;
 
        case PIPE_CAP_TGSI_TEXCOORD:
-               return 0;
+               return 1;
 
+       case PIPE_CAP_NIR_IMAGES_AS_DEREF:
        case PIPE_CAP_FAKE_SW_MSAA:
                return 0;
 
@@ -400,60 +409,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
                return 8;
 
-       /* Unsupported features. */
-       case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
-       case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
-       case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
-       case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
-       case PIPE_CAP_VERTEX_COLOR_CLAMPED:
-       case PIPE_CAP_USER_VERTEX_BUFFERS:
-       case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
-       case PIPE_CAP_VERTEXID_NOBASE:
-       case PIPE_CAP_DEPTH_BOUNDS_TEST:
-       case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
-       case PIPE_CAP_SHAREABLE_SHADERS:
-       case PIPE_CAP_DRAW_PARAMETERS:
-       case PIPE_CAP_MULTI_DRAW_INDIRECT:
-       case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
-       case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
-       case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
-       case PIPE_CAP_GENERATE_MIPMAP:
-       case PIPE_CAP_STRING_MARKER:
-       case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
-       case PIPE_CAP_TGSI_VOTE:
-       case PIPE_CAP_MAX_WINDOW_RECTANGLES:
-       case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
-       case PIPE_CAP_NATIVE_FENCE_FD:
        case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
-       case PIPE_CAP_FBFETCH:
-       case PIPE_CAP_INT64:
-       case PIPE_CAP_INT64_DIVMOD:
-       case PIPE_CAP_TGSI_TEX_TXF_LZ:
-       case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
-       case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
-       case PIPE_CAP_TGSI_BALLOT:
-       case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
-       case PIPE_CAP_POST_DEPTH_COVERAGE:
-       case PIPE_CAP_BINDLESS_TEXTURE:
-       case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
-       case PIPE_CAP_QUERY_SO_OVERFLOW:
-       case PIPE_CAP_MEMOBJ:
-       case PIPE_CAP_LOAD_CONSTBUF:
-       case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
-       case PIPE_CAP_TILE_RASTER_ORDER:
-       case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
-       case PIPE_CAP_CONTEXT_PRIORITY_MASK:
-       case PIPE_CAP_FENCE_SIGNAL:
-       case PIPE_CAP_CONSTBUF0_FLAGS:
-       case PIPE_CAP_PACKED_UNIFORMS:
-       case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
-       case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
-       case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
-       case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
-       case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
-       case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
-       case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
-       case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
                return 0;
 
        case PIPE_CAP_DOUBLES:
@@ -595,7 +551,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        {
        case PIPE_SHADER_FRAGMENT:
        case PIPE_SHADER_VERTEX:
-       case PIPE_SHADER_COMPUTE:
                break;
        case PIPE_SHADER_GEOMETRY:
                if (rscreen->b.family >= CHIP_CEDAR)
@@ -606,8 +561,10 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
                return 0;
        case PIPE_SHADER_TESS_CTRL:
        case PIPE_SHADER_TESS_EVAL:
+       case PIPE_SHADER_COMPUTE:
                if (rscreen->b.family >= CHIP_CEDAR)
                        break;
+               /* fallthrough */
        default:
                return 0;
        }
@@ -629,9 +586,11 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
                if (shader == PIPE_SHADER_COMPUTE) {
                        uint64_t max_const_buffer_size;
-                       pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
-                               PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
-                               &max_const_buffer_size);
+                       enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
+                               PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
+                       pscreen->get_compute_param(pscreen, ir_type,
+                                                  PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
+                                                  &max_const_buffer_size);
                        return MIN2(max_const_buffer_size, INT_MAX);
 
                } else {
@@ -651,6 +610,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_SUBROUTINES:
        case PIPE_SHADER_CAP_INT64_ATOMICS:
        case PIPE_SHADER_CAP_FP16:
+        case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+        case PIPE_SHADER_CAP_INT16:
+        case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
                return 0;
        case PIPE_SHADER_CAP_INTEGERS:
        case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
@@ -658,14 +620,19 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
                return 16;
-        case PIPE_SHADER_CAP_PREFERRED_IR:
+       case PIPE_SHADER_CAP_PREFERRED_IR:
+               if (is_nir_enabled(&rscreen->b))
+                       return PIPE_SHADER_IR_NIR;
                return PIPE_SHADER_IR_TGSI;
        case PIPE_SHADER_CAP_SUPPORTED_IRS: {
                int ir = 0;
                if (shader == PIPE_SHADER_COMPUTE)
                        ir = 1 << PIPE_SHADER_IR_NATIVE;
-               if (rscreen->b.family >= CHIP_CEDAR)
+               if (rscreen->b.family >= CHIP_CEDAR) {
                        ir |= 1 << PIPE_SHADER_IR_TGSI;
+                       if (is_nir_enabled(&rscreen->b))
+                               ir |= 1 << PIPE_SHADER_IR_NIR;
+               }
                return ir;
        }
        case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: