swr: fix build with mingw

[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 97f20355d599faf5b96cf4378dbe7c8edf8b9d25..eb26074221a635fb239b66347e5a792b02d88ea4 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -288,6 +288,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_VERTEX_SHADER_SATURATE:
        case PIPE_CAP_SEAMLESS_CUBE_MAP:
        case PIPE_CAP_PRIMITIVE_RESTART:
+       case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
        case PIPE_CAP_CONDITIONAL_RENDER:
        case PIPE_CAP_TEXTURE_BARRIER:
        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
@@ -323,6 +324,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
        case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+        case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
                return 1;
 
        case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
@@ -339,8 +341,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return rscreen->b.chip_class > R700;
 
        case PIPE_CAP_TGSI_TEXCOORD:
-               return is_nir_enabled(&rscreen->b);
+               return 1;
 
+       case PIPE_CAP_NIR_IMAGES_AS_DEREF:
        case PIPE_CAP_FAKE_SW_MSAA:
                return 0;
 
@@ -420,7 +423,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 1;
 
        case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
-               if (family >= CHIP_CEDAR && !is_nir_enabled(&rscreen->b))
+               if (family >= CHIP_CEDAR)
                        return 256;
                return 0;
 
@@ -556,15 +559,12 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
                if (rscreen->b.info.drm_minor >= 37)
                        break;
                return 0;
-      /* With NIR we currently disable TES, TCS and COMP shaders */
        case PIPE_SHADER_TESS_CTRL:
        case PIPE_SHADER_TESS_EVAL:
-               if (rscreen->b.family >= CHIP_CEDAR &&
-                   !is_nir_enabled(&rscreen->b))
-                       break;
        case PIPE_SHADER_COMPUTE:
-               if (!is_nir_enabled(&rscreen->b))
+               if (rscreen->b.family >= CHIP_CEDAR)
                        break;
+               /* fallthrough */
        default:
                return 0;
        }
@@ -610,6 +610,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
        case PIPE_SHADER_CAP_SUBROUTINES:
        case PIPE_SHADER_CAP_INT64_ATOMICS:
        case PIPE_SHADER_CAP_FP16:
+        case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+        case PIPE_SHADER_CAP_INT16:
+        case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
                return 0;
        case PIPE_SHADER_CAP_INTEGERS:
        case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: