bool cb0_is_integer;
bool is_msaa_resolve;
bool dual_src_blend;
+ bool do_update_surf_dirtiness;
};
struct r600_sample_mask {
bool scissor_enable;
bool multisample_enable;
bool clip_halfz;
+ bool rasterizer_discard;
};
struct r600_poly_offset_state {
enum pipe_shader_type type;
/* geometry shader properties */
- unsigned gs_output_prim;
- unsigned gs_max_out_vertices;
- unsigned gs_num_invocations;
+ enum pipe_prim_type gs_output_prim;
+ unsigned gs_max_out_vertices;
+ unsigned gs_num_invocations;
/* TCS/VS */
uint64_t lds_patch_outputs_written_mask;
* the GPU addresses are updated. */
struct list_head texture_buffers;
- /* Index buffer. */
- struct pipe_index_buffer index_buffer;
-
/* Last draw state (-1 = unset). */
enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
+ enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
+ enum pipe_prim_type last_rast_prim;
unsigned last_start_instance;
void *sb_context;
struct r600_pipe_shader_selector *last_tcs;
unsigned last_num_tcs_input_cp;
unsigned lds_alloc;
+
+ /* Debug state. */
+ bool is_debug;
+ struct radeon_saved_cs last_gfx;
+ struct r600_resource *last_trace_buf;
+ struct r600_resource *trace_buf;
+ unsigned trace_id;
};
static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
#define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
unsigned r600_conv_prim_to_gs_out(unsigned mode);
+
+void eg_trace_emit(struct r600_context *rctx);
+void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
+ unsigned flags);
#endif