#include "radeon/r600_pipe_common.h"
#include "radeon/r600_cs.h"
-
-#include "r600_llvm.h"
#include "r600_public.h"
+#include "pipe/p_defines.h"
#include "util/u_suballoc.h"
#include "util/list.h"
#include "util/u_transfer.h"
+#include "util/u_memory.h"
#include "tgsi/tgsi_scan.h"
#define R600_NUM_ATOMS 52
-#define R600_MAX_VIEWPORTS 16
-
/* read caches */
#define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
#define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
#define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
/* the number of CS dwords for flushing and drawing */
-#define R600_MAX_FLUSH_CS_DWORDS 16
+#define R600_MAX_FLUSH_CS_DWORDS 18
#define R600_MAX_DRAW_CS_DWORDS 58
-#define R600_TRACE_CS_DWORDS 7
+#define R600_MAX_PFP_SYNC_ME_DWORDS 16
#define R600_MAX_USER_CONST_BUFFERS 13
#define R600_MAX_DRIVER_CONST_BUFFERS 3
#define R600_NUM_HW_STAGES 4
#define EG_NUM_HW_STAGES 6
-#ifdef PIPE_ARCH_BIG_ENDIAN
-#define R600_BIG_ENDIAN 1
-#else
-#define R600_BIG_ENDIAN 0
-#endif
-
struct r600_context;
struct r600_bytecode;
union r600_shader_key;
struct r600_db_misc_state {
struct r600_atom atom;
- bool occlusion_query_enabled;
+ bool occlusion_queries_disabled;
bool flush_depthstencil_through_cb;
bool flush_depth_inplace;
bool flush_stencil_inplace;
bool export_16bpc;
bool cb0_is_integer;
bool is_msaa_resolve;
+ bool dual_src_blend;
+ bool do_update_surf_dirtiness;
};
struct r600_sample_mask {
struct pipe_stencil_ref pipe_state;
};
-struct r600_viewport_state {
- struct r600_atom atom;
- struct pipe_viewport_state state[R600_MAX_VIEWPORTS];
- uint32_t dirty_mask;
-};
-
struct r600_shader_stages_state {
struct r600_atom atom;
unsigned geom_enable;
/* This must start from 16. */
/* features */
-#define DBG_LLVM (1 << 29)
#define DBG_NO_CP_DMA (1 << 30)
/* shader backend */
#define DBG_NO_SB (1 << 21)
float offset_units;
float offset_scale;
bool offset_enable;
+ bool offset_units_unscaled;
bool scissor_enable;
bool multisample_enable;
+ bool clip_halfz;
+ bool rasterizer_discard;
};
struct r600_poly_offset_state {
enum pipe_format zs_format;
float offset_units;
float offset_scale;
+ bool offset_units_unscaled;
};
struct r600_blend_state {
unsigned num_shaders;
- /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
- unsigned type;
+ enum pipe_shader_type type;
/* geometry shader properties */
- unsigned gs_output_prim;
- unsigned gs_max_out_vertices;
- unsigned gs_num_invocations;
+ enum pipe_prim_type gs_output_prim;
+ unsigned gs_max_out_vertices;
+ unsigned gs_num_invocations;
/* TCS/VS */
uint64_t lds_patch_outputs_written_mask;
struct r600_command_buffer *cb;
};
-struct r600_scissor_state
-{
- struct r600_atom atom;
- struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS];
- uint32_t dirty_mask;
- bool enable; /* r6xx only */
-};
-
struct r600_fetch_shader {
struct r600_resource *buffer;
unsigned offset;
struct r600_poly_offset_state poly_offset_state;
struct r600_cso_state rasterizer_state;
struct r600_sample_mask sample_mask;
- struct r600_scissor_state scissor;
struct r600_seamless_cube_map seamless_cube_map;
struct r600_config_state config_state;
struct r600_stencil_ref_state stencil_ref;
struct r600_vgt_state vgt_state;
- struct r600_viewport_state viewport;
/* Shaders and shader resources. */
struct r600_cso_state vertex_fetch_shader;
struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
unsigned zwritemask;
int ps_iter_samples;
- /* Index buffer. */
- struct pipe_index_buffer index_buffer;
+ /* The list of all texture buffer objects in this context.
+ * This list is walked when a buffer is invalidated/reallocated and
+ * the GPU addresses are updated. */
+ struct list_head texture_buffers;
/* Last draw state (-1 = unset). */
- int last_primitive_type; /* Last primitive type used in draw_vbo. */
- int last_start_instance;
+ enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
+ enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
+ enum pipe_prim_type last_rast_prim;
+ unsigned last_start_instance;
void *sb_context;
struct r600_isa *isa;
struct r600_pipe_shader_selector *last_tcs;
unsigned last_num_tcs_input_cp;
unsigned lds_alloc;
+
+ /* Debug state. */
+ bool is_debug;
+ struct radeon_saved_cs last_gfx;
+ struct r600_resource *last_trace_buf;
+ struct r600_resource *trace_buf;
+ unsigned trace_id;
};
static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
struct r600_command_buffer *cb)
{
- assert(cs->cdw + cb->num_dw <= cs->max_dw);
- memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
- cs->cdw += cb->num_dw;
+ assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
+ memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
+ cs->current.cdw += cb->num_dw;
}
static inline void r600_set_atom_dirty(struct r600_context *rctx,
r600_set_atom_dirty(rctx, atom, true);
}
-void r600_trace_emit(struct r600_context *rctx);
-
static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
{
atom->emit(&rctx->b, atom);
r600_set_atom_dirty(rctx, atom, false);
- if (rctx->screen->b.trace_bo) {
- r600_trace_emit(rctx);
- }
}
static inline void r600_set_cso_state(struct r600_context *rctx,
void r600_begin_new_cs(struct r600_context *ctx);
void r600_flush_emit(struct r600_context *ctx);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
+void r600_emit_pfp_sync_me(struct r600_context *rctx);
void r600_cp_dma_copy_buffer(struct r600_context *rctx,
struct pipe_resource *dst, uint64_t dst_offset,
struct pipe_resource *src, uint64_t src_offset,
unsigned size);
void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
struct pipe_resource *dst, uint64_t offset,
- unsigned size, uint32_t clear_value);
+ unsigned size, uint32_t clear_value,
+ enum r600_coherency coher);
void r600_dma_copy_buffer(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
-void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
uint32_t r600_translate_stencil_op(int s_op);
uint32_t r600_translate_fill(uint32_t func);
unsigned r600_tex_wrap(unsigned wrap);
-unsigned r600_tex_filter(unsigned filter);
unsigned r600_tex_mipfilter(unsigned filter);
unsigned r600_tex_compare(unsigned compare);
bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
-struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
- struct pipe_resource *texture,
- const struct pipe_surface *templ,
- unsigned width, unsigned height);
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
const unsigned char *swizzle_view,
boolean vtx);
uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
const unsigned char *swizzle_view,
- uint32_t *word4_p, uint32_t *yuv_format_p);
-uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
-uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
+ uint32_t *word4_p, uint32_t *yuv_format_p,
+ bool do_endian_swap);
+uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
+ bool do_endian_swap);
+uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
/* r600_uvd.c */
struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
#define R600_LOOP_CONST_OFFSET 0X0003E200
#define EG_LOOP_CONST_OFFSET 0x0003A200
-#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
-#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
-#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
+#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
+#define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
+#define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
{
radeon_set_context_reg_seq(cs, reg, num);
/* Set the compute bit on the packet header */
- cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
+ cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
}
static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
assert(reg >= R600_CTL_CONST_OFFSET);
- assert(cs->cdw+2+num <= cs->max_dw);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
- cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
+ assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
+ radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
+ radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
}
static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
x >= 4096 ? 0xffff : x * 16;
}
-/* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
-static inline bool r600_can_read_depth(struct r600_texture *rtex)
+static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
{
- return rtex->resource.b.b.nr_samples <= 1 &&
- (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
- rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
+ switch (coher) {
+ default:
+ case R600_COHERENCY_NONE:
+ return 0;
+ case R600_COHERENCY_SHADER:
+ return R600_CONTEXT_INV_CONST_CACHE |
+ R600_CONTEXT_INV_VERTEX_CACHE |
+ R600_CONTEXT_INV_TEX_CACHE |
+ R600_CONTEXT_STREAMOUT_FLUSH;
+ case R600_COHERENCY_CB_META:
+ return R600_CONTEXT_FLUSH_AND_INV_CB |
+ R600_CONTEXT_FLUSH_AND_INV_CB_META;
+ }
}
#define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
#define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
unsigned r600_conv_prim_to_gs_out(unsigned mode);
+
+void eg_trace_emit(struct r600_context *rctx);
+void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
+ unsigned flags);
#endif