vc4: Add support for 16-bit signed/unsigned norm/scaled vertex attrs.

[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 4585ace155e5f55f0ce86d310a920ed43c0c43a3..46b0a2de07d010a0c2321bc8f0cd0aececd04143 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -26,13 +26,12 @@
 #ifndef R600_PIPE_H
 #define R600_PIPE_H
 
-#include "../radeon/r600_pipe_common.h"
-#include "../radeon/r600_cs.h"
+#include "radeon/r600_pipe_common.h"
+#include "radeon/r600_cs.h"
 
 #include "r600_llvm.h"
 #include "r600_public.h"
 
-#include "util/u_blitter.h"
 #include "util/u_suballoc.h"
 #include "util/u_double_list.h"
 #include "util/u_transfer.h"
@@ -41,20 +40,27 @@
 
 /* the number of CS dwords for flushing and drawing */
 #define R600_MAX_FLUSH_CS_DWORDS       16
-#define R600_MAX_DRAW_CS_DWORDS                37
+#define R600_MAX_DRAW_CS_DWORDS                40
 #define R600_TRACE_CS_DWORDS           7
 
 #define R600_MAX_USER_CONST_BUFFERS 13
-#define R600_MAX_DRIVER_CONST_BUFFERS 4
+#define R600_MAX_DRIVER_CONST_BUFFERS 3
 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
 
 /* start driver buffers after user buffers */
 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
-#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
-#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
-#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
+#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
+#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
+/* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
+ * of 16 const buffers.
+ * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
+ *
+ * In order to support d3d 11 mandated minimum of 15 user const buffers
+ * we'd have to squash all use cases into one driver buffer.
+ */
+#define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
 
-#define R600_MAX_CONST_BUFFER_SIZE 4096
+#define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
 
 #ifdef PIPE_ARCH_BIG_ENDIAN
 #define R600_BIG_ENDIAN 1
@@ -139,6 +145,7 @@ struct r600_clip_state {
 struct r600_cs_shader_state {
        struct r600_atom atom;
        unsigned kernel_index;
+       unsigned pc;
        struct r600_pipe_compute *shader;
 };
 
@@ -196,8 +203,8 @@ struct r600_gs_rings_state {
 
 /* This must start from 16. */
 /* features */
-#define DBG_LLVM               (1 << 17)
-#define DBG_NO_CP_DMA          (1 << 18)
+#define DBG_LLVM               (1 << 29)
+#define DBG_NO_CP_DMA          (1 << 30)
 /* shader backend */
 #define DBG_NO_SB              (1 << 21)
 #define DBG_SB_CS              (1 << 22)
@@ -222,6 +229,7 @@ struct r600_screen {
 
 struct r600_pipe_sampler_view {
        struct pipe_sampler_view        base;
+       struct list_head                list;
        struct r600_resource            *tex_resource;
        uint32_t                        tex_resource_words[8];
        bool                            skip_mip_address_reloc;
@@ -307,7 +315,6 @@ struct r600_samplerview_state {
        uint32_t                        dirty_mask;
        uint32_t                        compressed_depthtex_mask; /* which textures are depth */
        uint32_t                        compressed_colortex_mask;
-       boolean                         dirty_txq_constants;
        boolean                         dirty_buffer_constants;
 };
 
@@ -452,6 +459,7 @@ struct r600_context {
        bool                            force_blend_disable;
        boolean                         dual_src_blend;
        unsigned                        zwritemask;
+       int                                     ps_iter_samples;
 
        /* Index buffer. */
        struct pipe_index_buffer        index_buffer;
@@ -551,6 +559,13 @@ void r600_decompress_depth_textures(struct r600_context *rctx,
                                    struct r600_samplerview_state *textures);
 void r600_decompress_color_textures(struct r600_context *rctx,
                                    struct r600_samplerview_state *textures);
+void r600_resource_copy_region(struct pipe_context *ctx,
+                              struct pipe_resource *dst,
+                              unsigned dst_level,
+                              unsigned dstx, unsigned dsty, unsigned dstz,
+                              struct pipe_resource *src,
+                              unsigned src_level,
+                              const struct pipe_box *src_box);
 
 /* r600_shader.c */
 int r600_pipe_shader_create(struct pipe_context *ctx,
@@ -632,9 +647,7 @@ void r600_sampler_views_dirty(struct r600_context *rctx,
 void r600_sampler_states_dirty(struct r600_context *rctx,
                               struct r600_sampler_states *state);
 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
-void r600_draw_rectangle(struct blitter_context *blitter,
-                        int x1, int y1, int x2, int y2, float depth,
-                        enum blitter_attrib_type type, const union pipe_color_union *attrib);
+void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
 uint32_t r600_translate_stencil_op(int s_op);
 uint32_t r600_translate_fill(uint32_t func);
 unsigned r600_tex_wrap(unsigned wrap);