#ifndef R600_PIPE_H
#define R600_PIPE_H
+#include "../radeon/r600_pipe_common.h"
+#include "../radeon/r600_cs.h"
+
+#include "r600_llvm.h"
+#include "r600_public.h"
+#include "r600_resource.h"
+
#include "util/u_blitter.h"
#include "util/u_slab.h"
#include "util/u_suballoc.h"
#include "util/u_double_list.h"
#include "util/u_transfer.h"
-#include "r600_llvm.h"
-#include "r600_public.h"
-#include "r600_resource.h"
#define R600_NUM_ATOMS 41
#define R600_MAP_BUFFER_ALIGNMENT 64
-#define R600_ERR(fmt, args...) \
- fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
-
-/* read caches */
-#define R600_CONTEXT_INV_VERTEX_CACHE (1 << 0)
-#define R600_CONTEXT_INV_TEX_CACHE (1 << 1)
-#define R600_CONTEXT_INV_CONST_CACHE (1 << 2)
-/* read-write caches */
-#define R600_CONTEXT_STREAMOUT_FLUSH (1 << 8)
-#define R600_CONTEXT_FLUSH_AND_INV (1 << 9)
-#define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 10)
-#define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 11)
-#define R600_CONTEXT_FLUSH_AND_INV_DB (1 << 12)
-#define R600_CONTEXT_FLUSH_AND_INV_CB (1 << 13)
-/* engine synchronization */
-#define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 16)
-#define R600_CONTEXT_WAIT_3D_IDLE (1 << 17)
-#define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 18)
-
#define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
#define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
#define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
struct r600_bytecode;
struct r600_shader_key;
-/* This encapsulates a state or an operation which can emitted into the GPU
- * command stream. It's not limited to states only, it can be used for anything
- * that wants to write commands into the CS (e.g. cache flushes). */
-struct r600_atom {
- void (*emit)(struct r600_context *ctx, struct r600_atom *state);
- unsigned id;
- unsigned num_dw;
- bool dirty;
-};
-
/* This is an atom containing GPU commands that never change.
* This is supposed to be copied directly into the CS. */
struct r600_command_buffer {
struct pipe_viewport_state state;
};
-struct r600_pipe_fences {
- struct r600_resource *bo;
- unsigned *data;
- unsigned next_index;
- /* linked list of preallocated blocks */
- struct list_head blocks;
- /* linked list of freed fences */
- struct list_head pool;
- pipe_mutex mutex;
-};
-
-typedef boolean (*r600g_dma_blit_t)(struct pipe_context *ctx,
- struct pipe_resource *dst,
- unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src,
- unsigned src_level,
- const struct pipe_box *src_box);
-
-/* logging */
-#define DBG_TEX_DEPTH (1 << 0)
-#define DBG_COMPUTE (1 << 1)
-#define DBG_VM (1 << 2)
-#define DBG_TRACE_CS (1 << 3)
-/* shaders */
-#define DBG_FS (1 << 8)
-#define DBG_VS (1 << 9)
-#define DBG_GS (1 << 10)
-#define DBG_PS (1 << 11)
-#define DBG_CS (1 << 12)
+/* This must start from 16. */
/* features */
-#define DBG_NO_HYPERZ (1 << 16)
#define DBG_NO_LLVM (1 << 17)
#define DBG_NO_CP_DMA (1 << 18)
#define DBG_NO_ASYNC_DMA (1 << 19)
#define DBG_NO_DISCARD_RANGE (1 << 20)
/* shader backend */
-#define DBG_SB (1 << 21)
+#define DBG_NO_SB (1 << 21)
#define DBG_SB_CS (1 << 22)
#define DBG_SB_DRY_RUN (1 << 23)
#define DBG_SB_STAT (1 << 24)
#define DBG_SB_DISASM (1 << 27)
#define DBG_SB_SAFEMATH (1 << 28)
-struct r600_tiling_info {
- unsigned num_channels;
- unsigned num_banks;
- unsigned group_bytes;
-};
-
struct r600_screen {
- struct pipe_screen screen;
- struct radeon_winsys *ws;
- unsigned debug_flags;
- unsigned family;
- enum chip_class chip_class;
- struct radeon_info info;
- bool has_streamout;
+ struct r600_common_screen b;
bool has_msaa;
- bool has_cp_dma;
bool has_compressed_msaa_texturing;
- struct r600_tiling_info tiling_info;
- struct r600_pipe_fences fences;
/*for compute global memory binding, we allocate stuff here, instead of
* buffers.
struct r600_resource *trace_bo;
uint32_t *trace_ptr;
unsigned cs_count;
- r600g_dma_blit_t dma_blit;
-
- /* Auxiliary context. Mainly used to initialize resources.
- * It must be locked prior to using and flushed before unlocking. */
- struct pipe_context *aux_context;
- pipe_mutex aux_context_lock;
};
struct r600_pipe_sampler_view {
uint32_t *buffer_constants;
};
-struct r600_fence {
- struct pipe_reference reference;
- unsigned index; /* in the shared bo */
- struct r600_resource *sleep_bo;
- struct list_head head;
-};
-
-#define FENCE_BLOCK_SIZE 16
-
-struct r600_fence_block {
- struct r600_fence fences[FENCE_BLOCK_SIZE];
- struct list_head head;
-};
-
-#define R600_CONSTANT_ARRAY_SIZE 256
-#define R600_RESOURCE_ARRAY_SIZE 160
-
struct r600_constbuf_state
{
struct r600_atom atom;
uint64_t end_result;
};
-struct r600_so_target {
- struct pipe_stream_output_target b;
-
- /* The buffer where BUFFER_FILLED_SIZE is stored. */
- struct r600_resource *buf_filled_size;
- unsigned buf_filled_size_offset;
-
- unsigned stride_in_dw;
- unsigned so_index;
-};
-
-struct r600_streamout {
- struct r600_atom begin_atom;
- bool begin_emitted;
- unsigned num_dw_for_end;
-
- unsigned enabled_mask;
- unsigned num_targets;
- struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
-
- unsigned append_bitmask;
- bool suspended;
-};
-
-struct r600_ring {
- struct radeon_winsys_cs *cs;
- bool flushing;
- void (*flush)(void *ctx, unsigned flags);
-};
-
-struct r600_rings {
- struct r600_ring gfx;
- struct r600_ring dma;
-};
-
struct r600_context {
- struct pipe_context context;
+ struct r600_common_context b;
struct r600_screen *screen;
- struct radeon_winsys *ws;
- struct r600_rings rings;
struct blitter_context *blitter;
struct u_upload_mgr *uploader;
- struct u_suballocator *allocator_so_filled_size;
struct u_suballocator *allocator_fetch_shader;
struct util_slab_mempool pool_transfers;
unsigned initial_gfx_cs_size;
/* Hardware info. */
- enum radeon_family family;
- enum chip_class chip_class;
boolean has_vertex_cache;
boolean keep_tiling_flags;
unsigned default_ps_gprs, default_vs_gprs;
unsigned backend_mask;
unsigned max_db; /* for OQ */
- /* current unaccounted memory usage */
- uint64_t vram;
- uint64_t gtt;
-
/* Miscellaneous state objects. */
void *custom_dsa_flush;
void *custom_blend_resolve;
void *custom_blend_decompress;
+ void *custom_blend_fastclear;
/* With rasterizer discard, there doesn't have to be a pixel shader.
* In that case, we bind this one: */
void *dummy_pixel_shader;
struct r600_vertexbuf_state vertex_buffer_state;
/** Vertex buffers for compute shaders */
struct r600_vertexbuf_state cs_vertex_buffer_state;
- struct r600_streamout streamout;
/* Additional context states. */
- unsigned flags;
unsigned compute_cb_target_mask;
struct r600_pipe_shader_selector *ps_shader;
struct r600_pipe_shader_selector *vs_shader;
void *sb_context;
struct r600_isa *isa;
+
+ /* Work-around for flushing problems with compute shaders on Cayman:
+ * Emitting a SURFACE_SYNC packet with any of the CB*_DEST_BASE_ENA
+ * or DB_DEST_BASE_ENA bits set after dispatching a compute shader
+ * hangs the GPU.
+ *
+ * Setting this to true will prevent r600_flush_emit() from emitting
+ * a SURFACE_SYNC packet. This field will be cleared by
+ * by r600_context_flush() after flushing the command stream. */
+ boolean skip_surface_sync_on_next_cs_flush;
};
static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
{
- atom->emit(rctx, atom);
+ atom->emit(&rctx->b, atom);
atom->dirty = false;
if (rctx->screen->trace_bo) {
r600_trace_emit(rctx);
struct r600_command_buffer *cb)
{
state->cb = cb;
- state->atom.num_dw = cb->num_dw;
+ state->atom.num_dw = cb ? cb->num_dw : 0;
r600_set_cso_state(state, cso);
}
struct compute_memory_pool* compute_memory_pool_new(
struct r600_screen *rscreen);
+/* evergreen_compute.c */
+void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
+ unsigned start_slot, unsigned count,
+ struct pipe_sampler_view **views);
+
/* evergreen_state.c */
struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context *ctx,
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
void *evergreen_create_resolve_blend(struct r600_context *rctx);
void *evergreen_create_decompress_blend(struct r600_context *rctx);
+void *evergreen_create_fastclear_blend(struct r600_context *rctx);
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
void evergreen_update_db_shader_control(struct r600_context * rctx);
/* r600_blit.c */
-void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
- struct pipe_resource *src, const struct pipe_box *src_box);
-void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
- unsigned offset, unsigned size, unsigned char value);
void r600_init_blit_functions(struct r600_context *rctx);
-void r600_blit_decompress_depth(struct pipe_context *ctx,
- struct r600_texture *texture,
- struct r600_texture *staging,
- unsigned first_level, unsigned last_level,
- unsigned first_layer, unsigned last_layer,
- unsigned first_sample, unsigned last_sample);
void r600_decompress_depth_textures(struct r600_context *rctx,
struct r600_samplerview_state *textures);
void r600_decompress_color_textures(struct r600_context *rctx,
struct r600_samplerview_state *textures);
/* r600_buffer.c */
-bool r600_init_resource(struct r600_screen *rscreen,
- struct r600_resource *res,
- unsigned size, unsigned alignment,
- bool use_reusable_pool, unsigned usage);
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ,
unsigned alignment);
/* r600_pipe.c */
-boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
- struct radeon_winsys_cs_handle *buf,
- enum radeon_bo_usage usage);
-void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
- struct r600_resource *resource,
- unsigned usage);
const char * r600_llvm_gpu_string(enum radeon_family family);
unsigned usage);
void r600_update_db_shader_control(struct r600_context * rctx);
-/* r600_texture.c */
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-void r600_init_surface_functions(struct r600_context *r600);
-uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
- const unsigned char *swizzle_view,
- uint32_t *word4_p, uint32_t *yuv_format_p);
-struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
- struct pipe_resource *texture,
- const struct pipe_surface *templ,
- unsigned width, unsigned height);
-
-unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
- const unsigned char *swizzle_view,
- boolean vtx);
-
/* r600_hw_context.c */
void r600_get_backend_mask(struct r600_context *ctx);
void r600_context_flush(struct r600_context *ctx, unsigned flags);
void r600_begin_new_cs(struct r600_context *ctx);
-void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
- unsigned offset, unsigned value);
void r600_flush_emit(struct r600_context *ctx);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
uint64_t dst_offset,
uint64_t src_offset,
uint64_t size);
-boolean r600_dma_blit(struct pipe_context *ctx,
- struct pipe_resource *dst,
- unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src,
- unsigned src_level,
- const struct pipe_box *src_box);
-void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom);
-void r600_emit_streamout_end(struct r600_context *ctx);
-void r600_flag_resource_cache_flush(struct r600_context *rctx,
- struct pipe_resource *res);
/*
* evergreen_hw_context.c
*/
-void evergreen_flush_vgt_streamout(struct r600_context *ctx);
-void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit);
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
uint64_t dst_offset,
uint64_t src_offset,
uint64_t size);
-boolean evergreen_dma_blit(struct pipe_context *ctx,
- struct pipe_resource *dst,
- unsigned dst_level,
- unsigned dst_x, unsigned dst_y, unsigned dst_z,
- struct pipe_resource *src,
- unsigned src_level,
- const struct pipe_box *src_box);
/* r600_state_common.c */
void r600_init_common_state_functions(struct r600_context *rctx);
void r600_sampler_states_dirty(struct r600_context *rctx,
struct r600_sampler_states *state);
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
-void r600_streamout_buffers_dirty(struct r600_context *rctx);
void r600_draw_rectangle(struct blitter_context *blitter,
int x1, int y1, int x2, int y2, float depth,
enum blitter_attrib_type type, const union pipe_color_union *attrib);
unsigned r600_tex_mipfilter(unsigned filter);
unsigned r600_tex_compare(unsigned compare);
bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
+struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
+ struct pipe_resource *texture,
+ const struct pipe_surface *templ,
+ unsigned width, unsigned height);
+unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
+ const unsigned char *swizzle_view,
+ boolean vtx);
+uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
+ const unsigned char *swizzle_view,
+ uint32_t *word4_p, uint32_t *yuv_format_p);
/* r600_uvd.c */
-struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context,
- enum pipe_video_profile profile,
- enum pipe_video_entrypoint entrypoint,
- enum pipe_video_chroma_format chroma_format,
- unsigned width, unsigned height,
- unsigned max_references, bool expect_chunked_decode);
+struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
+ const struct pipe_video_codec *decoder);
struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
const struct pipe_video_buffer *tmpl);
-int r600_uvd_get_video_param(struct pipe_screen *screen,
- enum pipe_video_profile profile,
- enum pipe_video_cap param);
-
/*
* Helpers for building command buffers
*/
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
void r600_release_command_buffer(struct r600_command_buffer *cb);
-/*
- * Helpers for emitting state into a command stream directly.
- */
-static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
- struct r600_ring *ring,
- struct r600_resource *rbo,
- enum radeon_bo_usage usage)
-{
- assert(usage);
- /* make sure that all previous ring use are flushed so everything
- * look serialized from driver pov
- */
- if (!ring->flushing) {
- if (ring == &ctx->rings.gfx) {
- if (ctx->rings.dma.cs) {
- /* flush dma ring */
- ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
- }
- } else {
- /* flush gfx ring */
- ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
- }
- }
- return ctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage, rbo->domains) * 4;
-}
-
-static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
-{
- cs->buf[cs->cdw++] = value;
-}
-
-static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
-{
- assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
- memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
- cs->cdw += num;
-}
-
-static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
-{
- assert(reg < R600_CONTEXT_REG_OFFSET);
- assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
- cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
-}
-
-static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
-{
- assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
- assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
- cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
-}
-
static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
r600_write_context_reg_seq(cs, reg, num);
cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
}
-static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
-{
- r600_write_config_reg_seq(cs, reg, 1);
- r600_write_value(cs, value);
-}
-
-static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
-{
- r600_write_context_reg_seq(cs, reg, 1);
- r600_write_value(cs, value);
-}
-
static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
{
r600_write_compute_context_reg_seq(cs, reg, 1);
- r600_write_value(cs, value);
+ radeon_emit(cs, value);
}
static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
} else {
r600_write_context_reg(cs, reg, value);
}
-
}
+
static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
{
r600_write_ctl_const_seq(cs, reg, 1);
- r600_write_value(cs, value);
+ radeon_emit(cs, value);
}
/*
x >= 4096 ? 0xffff : x * 16;
}
-static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
-{
- struct r600_screen *rscreen = (struct r600_screen*)screen;
- struct r600_resource *rresource = (struct r600_resource*)resource;
-
- return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
-}
-
-static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_resource *rr = (struct r600_resource *)r;
-
- if (r == NULL) {
- return;
- }
-
- /*
- * The idea is to compute a gross estimate of memory requirement of
- * each draw call. After each draw call, memory will be precisely
- * accounted. So the uncertainty is only on the current draw call.
- * In practice this gave very good estimate (+/- 10% of the target
- * memory limit).
- */
- if (rr->domains & RADEON_DOMAIN_GTT) {
- rctx->gtt += rr->buf->size;
- }
- if (rr->domains & RADEON_DOMAIN_VRAM) {
- rctx->vram += rr->buf->size;
- }
-}
-
#endif
projects / mesa.git / blobdiff