#define R600_MAP_BUFFER_ALIGNMENT 64
-#define R600_ERR(fmt, args...) \
- fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
-
#define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
#define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
#define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
struct pipe_viewport_state state;
};
-struct r600_pipe_fences {
- struct r600_resource *bo;
- unsigned *data;
- unsigned next_index;
- /* linked list of preallocated blocks */
- struct list_head blocks;
- /* linked list of freed fences */
- struct list_head pool;
- pipe_mutex mutex;
-};
-
-/* features */
/* This must start from 16. */
-#define DBG_NO_HYPERZ (1 << 16)
+/* features */
#define DBG_NO_LLVM (1 << 17)
#define DBG_NO_CP_DMA (1 << 18)
#define DBG_NO_ASYNC_DMA (1 << 19)
#define DBG_SB_DISASM (1 << 27)
#define DBG_SB_SAFEMATH (1 << 28)
-struct r600_tiling_info {
- unsigned num_channels;
- unsigned num_banks;
- unsigned group_bytes;
-};
-
struct r600_screen {
struct r600_common_screen b;
- bool has_streamout;
bool has_msaa;
- bool has_cp_dma;
bool has_compressed_msaa_texturing;
- struct r600_tiling_info tiling_info;
- struct r600_pipe_fences fences;
/*for compute global memory binding, we allocate stuff here, instead of
* buffers.
uint32_t *buffer_constants;
};
-struct r600_fence {
- struct pipe_reference reference;
- unsigned index; /* in the shared bo */
- struct r600_resource *sleep_bo;
- struct list_head head;
-};
-
-#define FENCE_BLOCK_SIZE 16
-
-struct r600_fence_block {
- struct r600_fence fences[FENCE_BLOCK_SIZE];
- struct list_head head;
-};
-
struct r600_constbuf_state
{
struct r600_atom atom;
void *sb_context;
struct r600_isa *isa;
+
+ /* Work-around for flushing problems with compute shaders on Cayman:
+ * Emitting a SURFACE_SYNC packet with any of the CB*_DEST_BASE_ENA
+ * or DB_DEST_BASE_ENA bits set after dispatching a compute shader
+ * hangs the GPU.
+ *
+ * Setting this to true will prevent r600_flush_emit() from emitting
+ * a SURFACE_SYNC packet. This field will be cleared by
+ * by r600_context_flush() after flushing the command stream. */
+ boolean skip_surface_sync_on_next_cs_flush;
};
static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
struct r600_command_buffer *cb)
{
state->cb = cb;
- state->atom.num_dw = cb->num_dw;
+ state->atom.num_dw = cb ? cb->num_dw : 0;
r600_set_cso_state(state, cso);
}
struct compute_memory_pool* compute_memory_pool_new(
struct r600_screen *rscreen);
+/* evergreen_compute.c */
+void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
+ unsigned start_slot, unsigned count,
+ struct pipe_sampler_view **views);
+
/* evergreen_state.c */
struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context *ctx,
void evergreen_update_db_shader_control(struct r600_context * rctx);
/* r600_blit.c */
-void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
- struct pipe_resource *src, const struct pipe_box *src_box);
void r600_init_blit_functions(struct r600_context *rctx);
-void r600_blit_decompress_depth(struct pipe_context *ctx,
- struct r600_texture *texture,
- struct r600_texture *staging,
- unsigned first_level, unsigned last_level,
- unsigned first_layer, unsigned last_layer,
- unsigned first_sample, unsigned last_sample);
void r600_decompress_depth_textures(struct r600_context *rctx,
struct r600_samplerview_state *textures);
void r600_decompress_color_textures(struct r600_context *rctx,
struct r600_samplerview_state *textures);
/* r600_buffer.c */
-bool r600_init_resource(struct r600_screen *rscreen,
- struct r600_resource *res,
- unsigned size, unsigned alignment,
- bool use_reusable_pool, unsigned usage);
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ,
unsigned alignment);
/* r600_pipe.c */
-boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
- struct radeon_winsys_cs_handle *buf,
- enum radeon_bo_usage usage);
-void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
- struct r600_resource *resource,
- unsigned usage);
const char * r600_llvm_gpu_string(enum radeon_family family);
void r600_get_backend_mask(struct r600_context *ctx);
void r600_context_flush(struct r600_context *ctx, unsigned flags);
void r600_begin_new_cs(struct r600_context *ctx);
-void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
- unsigned offset, unsigned value);
void r600_flush_emit(struct r600_context *ctx);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
uint64_t dst_offset,
uint64_t src_offset,
uint64_t size);
-void r600_flag_resource_cache_flush(struct r600_context *rctx,
- struct pipe_resource *res);
/*
* evergreen_hw_context.c
projects / mesa.git / blobdiff