#ifndef R600_PIPE_H
#define R600_PIPE_H
-#include "util/u_blitter.h"
-#include "util/u_slab.h"
-#include "r600.h"
+#include "../radeon/r600_pipe_common.h"
+#include "../radeon/r600_cs.h"
+
#include "r600_llvm.h"
#include "r600_public.h"
-#include "r600_shader.h"
#include "r600_resource.h"
-#include "evergreen_compute.h"
-#define R600_NUM_ATOMS 32
+#include "util/u_blitter.h"
+#include "util/u_slab.h"
+#include "util/u_suballoc.h"
+#include "util/u_double_list.h"
+#include "util/u_transfer.h"
+
+#define R600_NUM_ATOMS 41
+
+/* the number of CS dwords for flushing and drawing */
+#define R600_MAX_FLUSH_CS_DWORDS 16
+#define R600_MAX_DRAW_CS_DWORDS 34
+#define R600_TRACE_CS_DWORDS 7
+
+#define R600_MAX_USER_CONST_BUFFERS 13
+#define R600_MAX_DRIVER_CONST_BUFFERS 3
+#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
+
+/* start driver buffers after user buffers */
+#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
+#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
+#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
-#define R600_MAX_CONST_BUFFERS 2
#define R600_MAX_CONST_BUFFER_SIZE 4096
#ifdef PIPE_ARCH_BIG_ENDIAN
#define R600_BIG_ENDIAN 0
#endif
-/* This encapsulates a state or an operation which can emitted into the GPU
- * command stream. It's not limited to states only, it can be used for anything
- * that wants to write commands into the CS (e.g. cache flushes). */
-struct r600_atom {
- void (*emit)(struct r600_context *ctx, struct r600_atom *state);
- unsigned id;
- unsigned num_dw;
- bool dirty;
-};
+#define R600_MAP_BUFFER_ALIGNMENT 64
+
+#define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
+#define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
+#define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
+#define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
+
+struct r600_context;
+struct r600_bytecode;
+struct r600_shader_key;
/* This is an atom containing GPU commands that never change.
* This is supposed to be copied directly into the CS. */
unsigned pkt_flags;
};
+struct r600_db_state {
+ struct r600_atom atom;
+ struct r600_surface *rsurf;
+};
+
struct r600_db_misc_state {
- struct r600_atom atom;
- bool occlusion_query_enabled;
- bool flush_depthstencil_through_cb;
- bool copy_depth, copy_stencil;
- unsigned copy_sample;
- unsigned log_samples;
+ struct r600_atom atom;
+ bool occlusion_query_enabled;
+ bool flush_depthstencil_through_cb;
+ bool flush_depthstencil_in_place;
+ bool copy_depth, copy_stencil;
+ unsigned copy_sample;
+ unsigned log_samples;
+ unsigned db_shader_control;
+ bool htile_clear;
};
struct r600_cb_misc_state {
struct r600_atom atom;
uint32_t vgt_multi_prim_ib_reset_en;
uint32_t vgt_multi_prim_ib_reset_indx;
-};
-
-struct r600_vgt2_state {
- struct r600_atom atom;
uint32_t vgt_indx_offset;
};
uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
};
+struct r600_config_state {
+ struct r600_atom atom;
+ unsigned sq_gpr_resource_mgmt_1;
+};
+
struct r600_stencil_ref
{
ubyte ref_value[2];
struct pipe_viewport_state state;
};
-enum r600_pipe_state_id {
- R600_PIPE_STATE_SCISSOR,
- R600_PIPE_STATE_RASTERIZER,
- R600_PIPE_STATE_DSA,
- R600_PIPE_NSTATES
-};
-
-struct compute_memory_pool;
-void compute_memory_pool_delete(struct compute_memory_pool* pool);
-struct compute_memory_pool* compute_memory_pool_new(
- struct r600_screen *rscreen);
-
-struct r600_pipe_fences {
- struct r600_resource *bo;
- unsigned *data;
- unsigned next_index;
- /* linked list of preallocated blocks */
- struct list_head blocks;
- /* linked list of freed fences */
- struct list_head pool;
- pipe_mutex mutex;
-};
+/* This must start from 16. */
+/* features */
+#define DBG_NO_LLVM (1 << 17)
+#define DBG_NO_CP_DMA (1 << 18)
+#define DBG_NO_ASYNC_DMA (1 << 19)
+#define DBG_NO_DISCARD_RANGE (1 << 20)
+/* shader backend */
+#define DBG_NO_SB (1 << 21)
+#define DBG_SB_CS (1 << 22)
+#define DBG_SB_DRY_RUN (1 << 23)
+#define DBG_SB_STAT (1 << 24)
+#define DBG_SB_DUMP (1 << 25)
+#define DBG_SB_NO_FALLBACK (1 << 26)
+#define DBG_SB_DISASM (1 << 27)
+#define DBG_SB_SAFEMATH (1 << 28)
struct r600_screen {
- struct pipe_screen screen;
- struct radeon_winsys *ws;
- unsigned family;
- enum chip_class chip_class;
- struct radeon_info info;
- bool has_streamout;
- struct r600_tiling_info tiling_info;
- struct r600_pipe_fences fences;
+ struct r600_common_screen b;
+ bool has_msaa;
+ bool has_compressed_msaa_texturing;
/*for compute global memory binding, we allocate stuff here, instead of
* buffers.
* XXX: Not sure if this is the best place for global_pool. Also,
* it's not thread safe, so it won't work with multiple contexts. */
struct compute_memory_pool *global_pool;
+ struct r600_resource *trace_bo;
+ uint32_t *trace_ptr;
+ unsigned cs_count;
};
struct r600_pipe_sampler_view {
struct pipe_sampler_view base;
struct r600_resource *tex_resource;
uint32_t tex_resource_words[8];
+ bool skip_mip_address_reloc;
};
-struct r600_pipe_rasterizer {
- struct r600_pipe_state rstate;
+struct r600_rasterizer_state {
+ struct r600_command_buffer buffer;
boolean flatshade;
boolean two_side;
unsigned sprite_coord_enable;
bool alpha_to_one;
};
-struct r600_pipe_dsa {
- struct r600_pipe_state rstate;
+struct r600_dsa_state {
+ struct r600_command_buffer buffer;
unsigned alpha_ref;
ubyte valuemask[2];
ubyte writemask[2];
- unsigned sx_alpha_test_control;
+ unsigned zwritemask;
+ unsigned sx_alpha_test_control;
};
struct r600_pipe_shader;
unsigned nr_ps_max_color_exports;
};
-struct r600_shader_key {
- unsigned color_two_side:1;
- unsigned alpha_to_one:1;
- unsigned nr_cbufs:4;
-};
-
-struct r600_pipe_shader {
- struct r600_pipe_shader_selector *selector;
- struct r600_pipe_shader *next_variant;
- struct r600_shader shader;
- struct r600_pipe_state rstate;
- struct r600_resource *bo;
- unsigned sprite_coord_enable;
- unsigned flatshade;
- unsigned pa_cl_vs_out_cntl;
- unsigned nr_ps_color_outputs;
- struct r600_shader_key key;
- unsigned db_shader_control;
- unsigned ps_depth_export;
-};
-
struct r600_pipe_sampler_state {
uint32_t tex_sampler_words[3];
- uint32_t border_color[4];
+ union pipe_color_union border_color;
bool border_color_use;
bool seamless_cube_map;
};
uint32_t dirty_mask;
uint32_t compressed_depthtex_mask; /* which textures are depth */
uint32_t compressed_colortex_mask;
+ boolean dirty_txq_constants;
+ boolean dirty_buffer_constants;
};
struct r600_sampler_states {
struct r600_samplerview_state views;
struct r600_sampler_states states;
bool is_array_sampler[NUM_TEX_UNITS];
-};
-struct r600_fence {
- struct pipe_reference reference;
- unsigned index; /* in the shared bo */
- struct r600_resource *sleep_bo;
- struct list_head head;
+ /* cube array txq workaround */
+ uint32_t *txq_constants;
+ /* buffer related workarounds */
+ uint32_t *buffer_constants;
};
-#define FENCE_BLOCK_SIZE 16
-
-struct r600_fence_block {
- struct r600_fence fences[FENCE_BLOCK_SIZE];
- struct list_head head;
-};
-
-#define R600_CONSTANT_ARRAY_SIZE 256
-#define R600_RESOURCE_ARRAY_SIZE 160
-
struct r600_constbuf_state
{
struct r600_atom atom;
struct r600_command_buffer *cb;
};
+struct r600_scissor_state
+{
+ struct r600_atom atom;
+ struct pipe_scissor_state scissor;
+ bool enable; /* r6xx only */
+};
+
+struct r600_fetch_shader {
+ struct r600_resource *buffer;
+ unsigned offset;
+};
+
+struct r600_shader_state {
+ struct r600_atom atom;
+ struct r600_pipe_shader_selector *shader;
+};
+
+struct r600_query_buffer {
+ /* The buffer where query results are stored. */
+ struct r600_resource *buf;
+ /* Offset of the next free result after current query data */
+ unsigned results_end;
+ /* If a query buffer is full, a new buffer is created and the old one
+ * is put in here. When we calculate the result, we sum up the samples
+ * from all buffers. */
+ struct r600_query_buffer *previous;
+};
+
+struct r600_query {
+ /* The query buffer and how many results are in it. */
+ struct r600_query_buffer buffer;
+ /* The type of query */
+ unsigned type;
+ /* Size of the result in memory for both begin_query and end_query,
+ * this can be one or two numbers, or it could even be a size of a structure. */
+ unsigned result_size;
+ /* The number of dwords for begin_query or end_query. */
+ unsigned num_cs_dw;
+ /* linked list of queries */
+ struct list_head list;
+ /* for custom non-GPU queries */
+ uint64_t begin_result;
+ uint64_t end_result;
+};
+
struct r600_context {
- struct pipe_context context;
+ struct r600_common_context b;
+ struct r600_screen *screen;
struct blitter_context *blitter;
- enum radeon_family family;
- enum chip_class chip_class;
+ struct u_upload_mgr *uploader;
+ struct u_suballocator *allocator_fetch_shader;
+ struct util_slab_mempool pool_transfers;
+ unsigned initial_gfx_cs_size;
+
+ /* Hardware info. */
boolean has_vertex_cache;
boolean keep_tiling_flags;
+ unsigned default_ps_gprs, default_vs_gprs;
unsigned r6xx_num_clause_temp_gprs;
+ unsigned backend_mask;
+ unsigned max_db; /* for OQ */
+
+ /* Miscellaneous state objects. */
void *custom_dsa_flush;
void *custom_blend_resolve;
void *custom_blend_decompress;
+ void *custom_blend_fastclear;
+ /* With rasterizer discard, there doesn't have to be a pixel shader.
+ * In that case, we bind this one: */
+ void *dummy_pixel_shader;
+ /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
+ * bug where valid CMASK and FMASK are required to be present to avoid
+ * a hardlock in certain operations but aren't actually used
+ * for anything useful. */
+ struct r600_resource *dummy_fmask;
+ struct r600_resource *dummy_cmask;
- struct r600_screen *screen;
- struct radeon_winsys *ws;
- struct r600_pipe_state *states[R600_PIPE_NSTATES];
- unsigned compute_cb_target_mask;
- unsigned db_shader_control;
- unsigned pa_sc_line_stipple;
- /* for saving when using blitter */
- struct pipe_scissor_state scissor;
- struct r600_pipe_shader_selector *ps_shader;
- struct r600_pipe_shader_selector *vs_shader;
- struct r600_pipe_rasterizer *rasterizer;
- struct r600_pipe_state spi;
- struct pipe_query *current_render_cond;
- unsigned current_render_cond_mode;
- /* shader information */
- boolean two_side;
- boolean spi_dirty;
- unsigned sprite_coord_enable;
- boolean flatshade;
- bool alpha_to_one;
- bool multisample_enable;
-
- struct u_upload_mgr *uploader;
- struct util_slab_mempool pool_transfers;
-
- unsigned default_ps_gprs, default_vs_gprs;
-
- /******************************/
- /* States based on r600_atom. */
+ /* State binding slots are here. */
struct r600_atom *atoms[R600_NUM_ATOMS];
/* States for CS initialization. */
struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
struct r600_clip_misc_state clip_misc_state;
struct r600_clip_state clip_state;
struct r600_db_misc_state db_misc_state;
+ struct r600_db_state db_state;
+ struct r600_cso_state dsa_state;
struct r600_framebuffer framebuffer;
struct r600_poly_offset_state poly_offset_state;
+ struct r600_cso_state rasterizer_state;
struct r600_sample_mask sample_mask;
+ struct r600_scissor_state scissor;
struct r600_seamless_cube_map seamless_cube_map;
+ struct r600_config_state config_state;
struct r600_stencil_ref_state stencil_ref;
struct r600_vgt_state vgt_state;
- struct r600_vgt2_state vgt2_state;
struct r600_viewport_state viewport;
/* Shaders and shader resources. */
struct r600_cso_state vertex_fetch_shader;
+ struct r600_shader_state vertex_shader;
+ struct r600_shader_state pixel_shader;
struct r600_cs_shader_state cs_shader_state;
struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
struct r600_textures_info samplers[PIPE_SHADER_TYPES];
struct r600_vertexbuf_state vertex_buffer_state;
/** Vertex buffers for compute shaders */
struct r600_vertexbuf_state cs_vertex_buffer_state;
- /******************************/
- bool force_blend_disable;
+ /* Additional context states. */
+ unsigned compute_cb_target_mask;
+ struct r600_pipe_shader_selector *ps_shader;
+ struct r600_pipe_shader_selector *vs_shader;
+ struct r600_rasterizer_state *rasterizer;
+ bool alpha_to_one;
+ bool force_blend_disable;
+ boolean dual_src_blend;
+ unsigned zwritemask;
- struct radeon_winsys_cs *cs;
+ /* Index buffer. */
+ struct pipe_index_buffer index_buffer;
- struct r600_range *range;
- unsigned nblocks;
- struct r600_block **blocks;
- struct list_head dirty;
- struct list_head enable_list;
- unsigned pm4_dirty_cdwords;
- unsigned ctx_pm4_ndwords;
+ /* Last draw state (-1 = unset). */
+ int last_primitive_type; /* Last primitive type used in draw_vbo. */
+ int last_start_instance;
+ /* Queries. */
/* The list of active queries. Only one query of each type can be active. */
- int num_occlusion_queries;
-
- /* Manage queries in two separate groups:
- * The timer ones and the others (streamout, occlusion).
- *
- * We do this because we should only suspend non-timer queries for u_blitter,
- * and later if the non-timer queries are suspended, the context flush should
- * only suspend and resume the timer queries. */
- struct list_head active_timer_queries;
- unsigned num_cs_dw_timer_queries_suspend;
- struct list_head active_nontimer_queries;
- unsigned num_cs_dw_nontimer_queries_suspend;
-
- bool timer_queries_suspended;
- bool nontimer_queries_suspended;
- bool streamout_suspended;
-
- unsigned num_cs_dw_streamout_end;
-
- unsigned backend_mask;
- unsigned max_db; /* for OQ */
- unsigned flags;
- boolean predicate_drawing;
-
- unsigned num_so_targets;
- struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
- boolean streamout_start;
- unsigned streamout_append_bitmask;
-
- /* There is no scissor enable bit on r6xx, so we must use a workaround.
- * This tracks if the scissor is enabled. */
- bool scissor_enable;
-
- /* With rasterizer discard, there doesn't have to be a pixel shader.
- * In that case, we bind this one: */
- void *dummy_pixel_shader;
+ int num_occlusion_queries;
+ int num_pipelinestat_queries;
+ /* Keep track of non-timer queries, because they should be suspended
+ * during context flushing.
+ * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
+ struct list_head active_nontimer_queries;
+ unsigned num_cs_dw_nontimer_queries_suspend;
+ /* If queries have been suspended. */
+ bool nontimer_queries_suspended;
+ unsigned num_draw_calls;
+
+ /* Render condition. */
+ struct pipe_query *current_render_cond;
+ unsigned current_render_cond_mode;
+ boolean current_render_cond_cond;
+ boolean predicate_drawing;
- boolean dual_src_blend;
+ void *sb_context;
+ struct r600_isa *isa;
- /* Index buffer. */
- struct pipe_index_buffer index_buffer;
-
- /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware
- * bug where valid CMASK and FMASK are required to be present to avoid
- * a hardlock in certain operations but aren't actually used
- * for anything useful. */
- struct r600_resource *dummy_fmask;
- struct r600_resource *dummy_cmask;
-
- /* Last draw state (-1 = unset). */
- int last_primitive_type; /* Last primitive type used in draw_vbo. */
- int last_start_instance;
+ /* Work-around for flushing problems with compute shaders on Cayman:
+ * Emitting a SURFACE_SYNC packet with any of the CB*_DEST_BASE_ENA
+ * or DB_DEST_BASE_ENA bits set after dispatching a compute shader
+ * hangs the GPU.
+ *
+ * Setting this to true will prevent r600_flush_emit() from emitting
+ * a SURFACE_SYNC packet. This field will be cleared by
+ * by r600_context_flush() after flushing the command stream. */
+ boolean skip_surface_sync_on_next_cs_flush;
};
static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
cs->cdw += cb->num_dw;
}
+void r600_trace_emit(struct r600_context *rctx);
+
static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
{
- atom->emit(rctx, atom);
+ atom->emit(&rctx->b, atom);
atom->dirty = false;
+ if (rctx->screen->trace_bo) {
+ r600_trace_emit(rctx);
+ }
}
static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
struct r600_command_buffer *cb)
{
state->cb = cb;
- state->atom.num_dw = cb->num_dw;
+ state->atom.num_dw = cb ? cb->num_dw : 0;
r600_set_cso_state(state, cso);
}
+/* compute_memory_pool.c */
+struct compute_memory_pool;
+void compute_memory_pool_delete(struct compute_memory_pool* pool);
+struct compute_memory_pool* compute_memory_pool_new(
+ struct r600_screen *rscreen);
+
+/* evergreen_compute.c */
+void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
+ unsigned start_slot, unsigned count,
+ struct pipe_sampler_view **views);
+
/* evergreen_state.c */
struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context *ctx,
enum chip_class ctx_chip_class,
enum radeon_family ctx_family,
int ctx_drm_minor);
+void cayman_init_common_regs(struct r600_command_buffer *cb,
+ enum chip_class ctx_chip_class,
+ enum radeon_family ctx_family,
+ int ctx_drm_minor);
void evergreen_init_state_functions(struct r600_context *rctx);
void evergreen_init_atom_start_cs(struct r600_context *rctx);
-void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
-void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
void *evergreen_create_resolve_blend(struct r600_context *rctx);
void *evergreen_create_decompress_blend(struct r600_context *rctx);
+void *evergreen_create_fastclear_blend(struct r600_context *rctx);
boolean evergreen_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
struct r600_surface *surf);
void evergreen_init_color_surface_rat(struct r600_context *rctx,
struct r600_surface *surf);
-void evergreen_update_dual_export_state(struct r600_context * rctx);
+void evergreen_update_db_shader_control(struct r600_context * rctx);
/* r600_blit.c */
-void r600_copy_buffer(struct pipe_context *ctx, struct
- pipe_resource *dst, unsigned dstx,
- struct pipe_resource *src, const struct pipe_box *src_box);
void r600_init_blit_functions(struct r600_context *rctx);
-void r600_blit_decompress_depth(struct pipe_context *ctx,
- struct r600_texture *texture,
- struct r600_texture *staging,
- unsigned first_level, unsigned last_level,
- unsigned first_layer, unsigned last_layer,
- unsigned first_sample, unsigned last_sample);
void r600_decompress_depth_textures(struct r600_context *rctx,
struct r600_samplerview_state *textures);
void r600_decompress_color_textures(struct r600_context *rctx,
struct r600_samplerview_state *textures);
/* r600_buffer.c */
-bool r600_init_resource(struct r600_screen *rscreen,
- struct r600_resource *res,
- unsigned size, unsigned alignment,
- unsigned bind, unsigned usage);
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ,
unsigned alignment);
/* r600_pipe.c */
-void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
- unsigned flags);
+const char * r600_llvm_gpu_string(enum radeon_family family);
+
/* r600_query.c */
void r600_init_query_functions(struct r600_context *rctx);
void r600_suspend_nontimer_queries(struct r600_context *ctx);
void r600_resume_nontimer_queries(struct r600_context *ctx);
-void r600_suspend_timer_queries(struct r600_context *ctx);
-void r600_resume_timer_queries(struct r600_context *ctx);
/* r600_resource.c */
void r600_init_context_resource_functions(struct r600_context *r600);
int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *shader,
struct r600_shader_key key);
-#ifdef HAVE_OPENCL
-int r600_compute_shader_create(struct pipe_context * ctx,
- LLVMModuleRef mod, struct r600_bytecode * bytecode);
-#endif
+
void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
/* r600_state.c */
struct pipe_resource *texture,
const struct pipe_sampler_view *state,
unsigned width_first_level, unsigned height_first_level);
-void r600_set_scissor_state(struct r600_context *rctx,
- const struct pipe_scissor_state *state);
void r600_init_state_functions(struct r600_context *rctx);
void r600_init_atom_start_cs(struct r600_context *rctx);
-void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
-void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
void *r600_create_db_flush_dsa(struct r600_context *rctx);
void *r600_create_resolve_blend(struct r600_context *rctx);
void *r700_create_resolve_blend(struct r600_context *rctx);
void *r600_create_decompress_blend(struct r600_context *rctx);
-void r600_adjust_gprs(struct r600_context *rctx);
+bool r600_adjust_gprs(struct r600_context *rctx);
boolean r600_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
unsigned sample_count,
unsigned usage);
-void r600_update_dual_export_state(struct r600_context * rctx);
-
-/* r600_texture.c */
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-void r600_init_surface_functions(struct r600_context *r600);
-uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
- const unsigned char *swizzle_view,
- uint32_t *word4_p, uint32_t *yuv_format_p);
-unsigned r600_texture_get_offset(struct r600_texture *rtex,
- unsigned level, unsigned layer);
-struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
- struct pipe_resource *texture,
- const struct pipe_surface *templ,
- unsigned width, unsigned height);
+void r600_update_db_shader_control(struct r600_context * rctx);
+
+/* r600_hw_context.c */
+void r600_get_backend_mask(struct r600_context *ctx);
+void r600_context_flush(struct r600_context *ctx, unsigned flags);
+void r600_begin_new_cs(struct r600_context *ctx);
+void r600_flush_emit(struct r600_context *ctx);
+void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
+void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
+void r600_cp_dma_copy_buffer(struct r600_context *rctx,
+ struct pipe_resource *dst, uint64_t dst_offset,
+ struct pipe_resource *src, uint64_t src_offset,
+ unsigned size);
+void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
+ struct pipe_resource *dst, uint64_t offset,
+ unsigned size, uint32_t clear_value);
+void r600_dma_copy(struct r600_context *rctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
-/* r600_translate.c */
-void r600_translate_index_buffer(struct r600_context *r600,
- struct pipe_index_buffer *ib,
- unsigned count);
+/*
+ * evergreen_hw_context.c
+ */
+void evergreen_dma_copy(struct r600_context *rctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
/* r600_state_common.c */
void r600_init_common_state_functions(struct r600_context *rctx);
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
-void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
+void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
void (*emit)(struct r600_context *ctx, struct r600_atom *state),
unsigned num_dw);
struct r600_samplerview_state *state);
void r600_sampler_states_dirty(struct r600_context *rctx,
struct r600_sampler_states *state);
-void r600_set_max_scissor(struct r600_context *rctx);
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
void r600_draw_rectangle(struct blitter_context *blitter,
int x1, int y1, int x2, int y2, float depth,
unsigned r600_tex_filter(unsigned filter);
unsigned r600_tex_mipfilter(unsigned filter);
unsigned r600_tex_compare(unsigned compare);
+bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
+struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
+ struct pipe_resource *texture,
+ const struct pipe_surface *templ,
+ unsigned width, unsigned height);
+unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
+ const unsigned char *swizzle_view,
+ boolean vtx);
+uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
+ const unsigned char *swizzle_view,
+ uint32_t *word4_p, uint32_t *yuv_format_p);
+
+/* r600_uvd.c */
+struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
+ const struct pipe_video_codec *decoder);
+
+struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
+ const struct pipe_video_buffer *tmpl);
/*
* Helpers for building command buffers
cb->buf[cb->num_dw++] = value;
}
+static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
+{
+ assert(cb->num_dw+num <= cb->max_num_dw);
+ memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
+ cb->num_dw += num;
+}
+
static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
{
assert(reg < R600_CONTEXT_REG_OFFSET);
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
void r600_release_command_buffer(struct r600_command_buffer *cb);
-/*
- * Helpers for emitting state into a command stream directly.
- */
-
-static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
- enum radeon_bo_usage usage)
-{
- assert(usage);
- return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
-}
-
-static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
-{
- cs->buf[cs->cdw++] = value;
-}
-
-static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
-{
- assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
- memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
- cs->cdw += num;
-}
-
-static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
-{
- assert(reg < R600_CONTEXT_REG_OFFSET);
- assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
- cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
-}
-
-static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
-{
- assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
- assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
- cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
- cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
-}
-
static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
r600_write_context_reg_seq(cs, reg, num);
cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
}
-static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
-{
- r600_write_config_reg_seq(cs, reg, 1);
- r600_write_value(cs, value);
-}
-
-static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
{
- r600_write_context_reg_seq(cs, reg, 1);
- r600_write_value(cs, value);
+ r600_write_compute_context_reg_seq(cs, reg, 1);
+ radeon_emit(cs, value);
}
-static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
{
- r600_write_compute_context_reg_seq(cs, reg, 1);
- r600_write_value(cs, value);
+ if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
+ r600_write_compute_context_reg(cs, reg, value);
+ } else {
+ r600_write_context_reg(cs, reg, value);
+ }
}
static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
{
r600_write_ctl_const_seq(cs, reg, 1);
- r600_write_value(cs, value);
+ radeon_emit(cs, value);
}
/*
x >= 4096 ? 0xffff : x * 16;
}
-static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
-{
- struct r600_screen *rscreen = (struct r600_screen*)screen;
- struct r600_resource *rresource = (struct r600_resource*)resource;
-
- return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
-}
-
#endif
projects / mesa.git / blobdiff