#include "r600_resource.h"
#include "evergreen_compute.h"
-#define R600_NUM_ATOMS 37
+#define R600_NUM_ATOMS 38
#define R600_TRACE_CS 0
-#define R600_MAX_USER_CONST_BUFFERS 1
-#define R600_MAX_DRIVER_CONST_BUFFERS 2
+#define R600_MAX_USER_CONST_BUFFERS 13
+#define R600_MAX_DRIVER_CONST_BUFFERS 3
#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
/* start driver buffers after user buffers */
#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
+#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
#define R600_MAX_CONST_BUFFER_SIZE 4096
struct r600_atom atom;
uint32_t vgt_multi_prim_ib_reset_en;
uint32_t vgt_multi_prim_ib_reset_indx;
-};
-
-struct r600_vgt2_state {
- struct r600_atom atom;
uint32_t vgt_indx_offset;
};
MSAA_TEXTURE_COMPRESSED
};
+typedef boolean (*r600g_dma_blit_t)(struct pipe_context *ctx,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dst_x, unsigned dst_y, unsigned dst_z,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box);
+
struct r600_screen {
struct pipe_screen screen;
struct radeon_winsys *ws;
struct radeon_info info;
bool has_streamout;
bool has_msaa;
+ bool has_cp_dma;
enum r600_msaa_texture_mode msaa_texture_support;
bool use_hyperz;
struct r600_tiling_info tiling_info;
uint32_t *trace_ptr;
unsigned cs_count;
#endif
+ r600g_dma_blit_t dma_blit;
};
struct r600_pipe_sampler_view {
unsigned alpha_ref;
ubyte valuemask[2];
ubyte writemask[2];
- unsigned sx_alpha_test_control;
+ unsigned zwritemask;
+ unsigned sx_alpha_test_control;
};
struct r600_pipe_shader;
uint32_t compressed_depthtex_mask; /* which textures are depth */
uint32_t compressed_colortex_mask;
boolean dirty_txq_constants;
+ boolean dirty_buffer_constants;
};
struct r600_sampler_states {
/* cube array txq workaround */
uint32_t *txq_constants;
+ /* buffer related workarounds */
+ uint32_t *buffer_constants;
};
struct r600_fence {
unsigned offset;
};
+struct r600_streamout {
+ struct r600_atom begin_atom;
+ bool begin_emitted;
+ unsigned num_dw_for_end;
+
+ unsigned enabled_mask;
+ unsigned num_targets;
+ struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
+
+ unsigned append_bitmask;
+ bool suspended;
+};
+
+struct r600_ring {
+ struct radeon_winsys_cs *cs;
+ bool flushing;
+ void (*flush)(void *ctx, unsigned flags);
+};
+
+struct r600_rings {
+ struct r600_ring gfx;
+ struct r600_ring dma;
+};
+
struct r600_context {
struct pipe_context context;
struct r600_screen *screen;
struct radeon_winsys *ws;
- struct radeon_winsys_cs *cs;
+ struct r600_rings rings;
struct blitter_context *blitter;
- struct u_upload_mgr *uploader;
+ struct u_upload_mgr *uploader;
struct u_suballocator *allocator_so_filled_size;
struct u_suballocator *allocator_fetch_shader;
struct util_slab_mempool pool_transfers;
unsigned backend_mask;
unsigned max_db; /* for OQ */
+ /* current unaccounted memory usage */
+ uint64_t vram;
+ uint64_t gtt;
+
/* Miscellaneous state objects. */
void *custom_dsa_flush;
void *custom_blend_resolve;
struct r600_config_state config_state;
struct r600_stencil_ref_state stencil_ref;
struct r600_vgt_state vgt_state;
- struct r600_vgt2_state vgt2_state;
struct r600_viewport_state viewport;
/* Shaders and shader resources. */
struct r600_cso_state vertex_fetch_shader;
struct r600_vertexbuf_state vertex_buffer_state;
/** Vertex buffers for compute shaders */
struct r600_vertexbuf_state cs_vertex_buffer_state;
+ struct r600_streamout streamout;
/* Additional context states. */
unsigned flags;
bool alpha_to_one;
bool force_blend_disable;
boolean dual_src_blend;
+ unsigned zwritemask;
/* Index buffer. */
struct pipe_index_buffer index_buffer;
unsigned current_render_cond_mode;
boolean predicate_drawing;
- /* Streamout state. */
- unsigned num_cs_dw_streamout_end;
- unsigned num_so_targets;
- struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
- boolean streamout_start;
- unsigned streamout_append_bitmask;
- bool streamout_suspended;
-
/* Deprecated state management. */
struct r600_range *range;
unsigned nblocks;
struct list_head dirty;
struct list_head enable_list;
unsigned pm4_dirty_cdwords;
+
+ struct r600_isa *isa;
};
static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
void evergreen_update_db_shader_control(struct r600_context * rctx);
/* r600_blit.c */
-void r600_copy_buffer(struct pipe_context *ctx, struct
- pipe_resource *dst, unsigned dstx,
+void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
struct pipe_resource *src, const struct pipe_box *src_box);
void r600_init_blit_functions(struct r600_context *rctx);
void r600_blit_decompress_depth(struct pipe_context *ctx,
unsigned alignment);
/* r600_pipe.c */
-void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
- unsigned flags);
+boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
+ struct radeon_winsys_cs_handle *buf,
+ enum radeon_bo_usage usage);
+void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
+ struct r600_resource *resource,
+ unsigned usage);
/* r600_query.c */
void r600_init_query_functions(struct r600_context *rctx);
const struct pipe_surface *templ,
unsigned width, unsigned height);
+unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
+ const unsigned char *swizzle_view,
+ boolean vtx);
+
+/* r600_hw_context.c */
+void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom);
+void r600_emit_streamout_end(struct r600_context *ctx);
+
/* r600_state_common.c */
void r600_init_common_state_functions(struct r600_context *rctx);
void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
-void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_sampler_states_dirty(struct r600_context *rctx,
struct r600_sampler_states *state);
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
+void r600_streamout_buffers_dirty(struct r600_context *rctx);
void r600_draw_rectangle(struct blitter_context *blitter,
int x1, int y1, int x2, int y2, float depth,
enum blitter_attrib_type type, const union pipe_color_union *attrib);
/*
* Helpers for emitting state into a command stream directly.
*/
-
-static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
+static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
+ struct r600_ring *ring,
+ struct r600_resource *rbo,
enum radeon_bo_usage usage)
{
assert(usage);
- return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
+ /* make sure that all previous ring use are flushed so everything
+ * look serialized from driver pov
+ */
+ if (!ring->flushing) {
+ if (ring == &ctx->rings.gfx) {
+ if (ctx->rings.dma.cs) {
+ /* flush dma ring */
+ ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
+ } else {
+ /* flush gfx ring */
+ ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
+ }
+ return ctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage, rbo->domains) * 4;
}
static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
}
-static INLINE unsigned u_max_layer(struct pipe_resource *r, unsigned level)
-{
- switch (r->target) {
- case PIPE_TEXTURE_CUBE:
- return 6 - 1;
- case PIPE_TEXTURE_3D:
- return u_minify(r->depth0, level) - 1;
- case PIPE_TEXTURE_1D_ARRAY:
- case PIPE_TEXTURE_2D_ARRAY:
- case PIPE_TEXTURE_CUBE_ARRAY:
- return r->array_size - 1;
- default:
- return 0;
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource *rr = (struct r600_resource *)r;
+
+ if (r == NULL) {
+ return;
+ }
+
+ /*
+ * The idea is to compute a gross estimate of memory requirement of
+ * each draw call. After each draw call, memory will be precisely
+ * accounted. So the uncertainty is only on the current draw call.
+ * In practice this gave very good estimate (+/- 10% of the target
+ * memory limit).
+ */
+ if (rr->domains & RADEON_DOMAIN_GTT) {
+ rctx->gtt += rr->buf->size;
+ }
+ if (rr->domains & RADEON_DOMAIN_VRAM) {
+ rctx->vram += rr->buf->size;
}
}
projects / mesa.git / blobdiff