}
}
-static void emit_sample_streamout(struct radeon_winsys_cs *cs, uint64_t va,
+static void emit_sample_streamout(struct radeon_cmdbuf *cs, uint64_t va,
unsigned stream)
{
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
struct r600_resource *buffer,
uint64_t va)
{
- struct radeon_winsys_cs *cs = ctx->gfx.cs;
+ struct radeon_cmdbuf *cs = ctx->gfx.cs;
switch (query->b.type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
struct r600_resource *buffer,
uint64_t va)
{
- struct radeon_winsys_cs *cs = ctx->gfx.cs;
+ struct radeon_cmdbuf *cs = ctx->gfx.cs;
uint64_t fence_va = 0;
switch (query->b.type) {
struct r600_resource *buf, uint64_t va,
uint32_t op)
{
- struct radeon_winsys_cs *cs = ctx->gfx.cs;
+ struct radeon_cmdbuf *cs = ctx->gfx.cs;
radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
radeon_emit(cs, va);
{
struct r600_common_context *ctx =
(struct r600_common_context*)rscreen->aux_context;
- struct radeon_winsys_cs *cs = ctx->gfx.cs;
+ struct radeon_cmdbuf *cs = ctx->gfx.cs;
struct r600_resource *buffer;
uint32_t *results;
unsigned i, mask = 0;