r600g: split flushed depth texture creation and flushing

[mesa.git] / src / gallium / drivers / r600 / r600_resource.h

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 5120e27865ceead615d4af8714cea7ace9e29964..13fce002df50e2af8ce3f81d64b69cba63d61c0c 100644 (file)
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -23,20 +23,22 @@
 #ifndef R600_RESOURCE_H
 #define R600_RESOURCE_H
 
-#include "util/u_transfer.h"
-#include "util/u_vbuf_mgr.h"
+#include "r600.h"
 
 /* flag to indicate a resource is to be used as a transfer so should not be tiled */
 #define R600_RESOURCE_FLAG_TRANSFER     PIPE_RESOURCE_FLAG_DRV_PRIV
 
-/* Texture transfer. */
 struct r600_transfer {
-       /* Base class. */
        struct pipe_transfer            transfer;
-       /* Buffer transfer. */
-       struct pipe_transfer            *buffer_transfer;
+       struct r600_resource            *staging;
        unsigned                        offset;
-       struct pipe_resource            *staging_texture;
+};
+
+struct compute_memory_item;
+
+struct r600_resource_global {
+       struct r600_resource base;
+       struct compute_memory_item *chunk;
 };
 
 struct r600_resource_texture {
@@ -55,15 +57,12 @@ struct r600_resource_texture {
        unsigned                        pitch_override;
        unsigned                        size;
        unsigned                        tile_type;
-       unsigned                        depth;
+       bool                            is_depth;
        unsigned                        dirty_db;
        struct r600_resource_texture    *stencil; /* Stencil is in a separate buffer on Evergreen. */
        struct r600_resource_texture    *flushed_depth_texture;
        boolean                         is_flushing_texture;
-
-       /* on some cards we have to use integer 64/128-bit types
-          for s3tc blits, do this until gallium grows int formats */
-       boolean force_int_type;
+       struct radeon_surface           surface;
 };
 
 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
@@ -73,6 +72,7 @@ struct r600_surface {
        unsigned                        aligned_height;
 };
 
+void r600_resource_destroy(struct pipe_screen *screen, struct pipe_resource *res);
 void r600_init_screen_resource_functions(struct pipe_screen *screen);
 
 /* r600_texture */
@@ -87,7 +87,10 @@ static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
        return (struct r600_resource*)r;
 }
 
-int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource *texture, boolean just_create);
+void r600_init_flushed_depth_texture(struct pipe_context *ctx,
+                                    struct pipe_resource *texture);
+void r600_texture_depth_flush(struct pipe_context *ctx,
+                             struct pipe_resource *texture);
 
 /* r600_texture.c texture transfer functions. */
 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
@@ -102,8 +105,4 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
                                 struct pipe_transfer* transfer);
 
-struct r600_pipe_context;
-
-void r600_upload_const_buffer(struct r600_pipe_context *rctx, struct r600_resource **rbuffer, uint32_t *offset);
-
 #endif