r600g: drop width/height per level storage.

[mesa.git] / src / gallium / drivers / r600 / r600_resource.h

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index cd1c31e82d0176c11d9c4a5985e52cde1ee265f1..323960960d628bc20c2655c486096f35da815e31 100644 (file)
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -25,8 +25,15 @@
 
 #include "util/u_transfer.h"
 
-struct r600_context;
-struct r600_screen;
+/* Texture transfer. */
+struct r600_transfer {
+       /* Base class. */
+       struct pipe_transfer            transfer;
+       /* Buffer transfer. */
+       struct pipe_transfer            *buffer_transfer;
+       unsigned                        offset;
+       struct pipe_resource            *linear_texture;
+};
 
 /* This gets further specialized into either buffer or texture
  * structures. Use the vtbl struct to choose between the two
@@ -34,7 +41,7 @@ struct r600_screen;
  */
 struct r600_resource {
        struct u_resource               base;
-       struct radeon_ws_bo             *bo;
+       struct r600_bo                  *bo;
        u32                             domain;
        u32                             flink;
        u32                             size;
@@ -44,25 +51,18 @@ struct r600_resource_texture {
        struct r600_resource            resource;
        unsigned long                   offset[PIPE_MAX_TEXTURE_LEVELS];
        unsigned long                   pitch[PIPE_MAX_TEXTURE_LEVELS];
-       unsigned long                   width[PIPE_MAX_TEXTURE_LEVELS];
-       unsigned long                   height[PIPE_MAX_TEXTURE_LEVELS];
        unsigned long                   layer_size[PIPE_MAX_TEXTURE_LEVELS];
        unsigned long                   pitch_override;
        unsigned long                   bpt;
        unsigned long                   size;
-       unsigned                        tilled;
+       unsigned                        tiled;
        unsigned                        array_mode;
        unsigned                        tile_type;
        unsigned                        depth;
        unsigned                        dirty;
-       struct radeon_ws_bo             *uncompressed;
-       struct radeon_state             scissor[PIPE_MAX_TEXTURE_LEVELS];
-       struct radeon_state             cb[8][PIPE_MAX_TEXTURE_LEVELS];
-       struct radeon_state             db[PIPE_MAX_TEXTURE_LEVELS];
-       struct radeon_state             viewport[PIPE_MAX_TEXTURE_LEVELS];
+       struct r600_resource_texture    *flushed_depth_texture;
 };
 
-void r600_init_context_resource_functions(struct r600_context *r600);
 void r600_init_screen_resource_functions(struct pipe_screen *screen);
 
 /* r600_buffer */
@@ -106,4 +106,22 @@ static INLINE boolean r600_buffer_is_user_buffer(struct pipe_resource *buffer)
     return r600_buffer(buffer)->user_buffer ? TRUE : FALSE;
 }
 
+int r600_texture_depth_flush(struct pipe_context *ctx,
+                            struct pipe_resource *texture);
+
+extern int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
+
+/* r600_texture.c texture transfer functions. */
+struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
+                                               struct pipe_resource *texture,
+                                               struct pipe_subresource sr,
+                                               unsigned usage,
+                                               const struct pipe_box *box);
+void r600_texture_transfer_destroy(struct pipe_context *ctx,
+                                  struct pipe_transfer *trans);
+void* r600_texture_transfer_map(struct pipe_context *ctx,
+                               struct pipe_transfer* transfer);
+void r600_texture_transfer_unmap(struct pipe_context *ctx,
+                                struct pipe_transfer* transfer);
+
 #endif