r600g/sb: fix debug dump code in scheduler

[mesa.git] / src / gallium / drivers / r600 / r600_resource.h

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index bf7fffa44c5ade56ece363948090e0ec72c9b4d5..4c55f66e50c4f3e33cde0d5c5405eac22c96e89c 100644 (file)
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -23,11 +23,36 @@
 #ifndef R600_RESOURCE_H
 #define R600_RESOURCE_H
 
-#include "r600.h"
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "util/u_range.h"
+
+struct r600_screen;
 
 /* flag to indicate a resource is to be used as a transfer so should not be tiled */
 #define R600_RESOURCE_FLAG_TRANSFER            PIPE_RESOURCE_FLAG_DRV_PRIV
 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH       (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+#define R600_RESOURCE_FLAG_FORCE_TILING                (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+
+struct r600_resource {
+       struct u_resource               b;
+
+       /* Winsys objects. */
+       struct pb_buffer                *buf;
+       struct radeon_winsys_cs_handle  *cs_buf;
+
+       /* Resource state. */
+       enum radeon_bo_domain           domains;
+
+       /* The buffer range which is initialized (with a write transfer,
+        * streamout, DMA, or as a random access target). The rest of
+        * the buffer is considered invalid and can be mapped unsynchronized.
+        *
+        * This allows unsychronized mapping of a buffer range which hasn't
+        * been used yet. It's for applications which forget to use
+        * the unsynchronized map flag and expect the driver to figure it out.
+         */
+       struct util_range               valid_buffer_range;
+};
 
 struct r600_transfer {
        struct pipe_transfer            transfer;
@@ -48,7 +73,7 @@ struct r600_texture {
        unsigned                        array_mode[PIPE_MAX_TEXTURE_LEVELS];
        unsigned                        pitch_override;
        unsigned                        size;
-       unsigned                        tile_type;
+       bool                            non_disp_tiling;
        bool                            is_depth;
        bool                            is_rat;
        unsigned                        dirty_level_mask; /* each bit says if that mipmap is compressed */
@@ -59,7 +84,15 @@ struct r600_texture {
        /* FMASK and CMASK can only be used with MSAA textures for now.
         * MSAA textures cannot have mipmaps. */
        unsigned                        fmask_offset, fmask_size, fmask_bank_height;
-       unsigned                        cmask_offset, cmask_size, cmask_slice_tile_max;
+       unsigned                        fmask_slice_tile_max;
+       unsigned                        cmask_offset, cmask_size;
+       unsigned                        cmask_slice_tile_max;
+
+       struct r600_resource            *htile;
+       /* use htile only for first level */
+       float                           depth_clear;
+
+       unsigned                        color_clear_value[2];
 };
 
 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
@@ -68,6 +101,7 @@ struct r600_fmask_info {
        unsigned size;
        unsigned alignment;
        unsigned bank_height;
+       unsigned slice_tile_max;
 };
 
 struct r600_cmask_info {
@@ -113,8 +147,21 @@ struct r600_surface {
        unsigned db_stencil_info;       /* EG only */
        unsigned db_prefetch_limit;     /* R600 only */
        unsigned pa_su_poly_offset_db_fmt_cntl;
+
+       unsigned                        htile_enabled;
+       unsigned                        db_htile_surface;
+       unsigned                        db_htile_data_base;
+       unsigned                        db_preload_control;
 };
 
+/* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
+static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
+{
+       return rtex->resource.b.b.nr_samples <= 1 &&
+              (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
+               rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
+}
+
 void r600_resource_destroy(struct pipe_screen *screen, struct pipe_resource *res);
 void r600_init_screen_resource_functions(struct pipe_screen *screen);
 
@@ -141,17 +188,4 @@ bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
                                     struct pipe_resource *texture,
                                     struct r600_texture **staging);
 
-/* r600_texture.c texture transfer functions. */
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
-                                               struct pipe_resource *texture,
-                                               unsigned level,
-                                               unsigned usage,
-                                               const struct pipe_box *box);
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
-                                  struct pipe_transfer *trans);
-void* r600_texture_transfer_map(struct pipe_context *ctx,
-                               struct pipe_transfer* transfer);
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
-                                struct pipe_transfer* transfer);
-
 #endif