r600g: move streamout state to drivers/radeon

[mesa.git] / src / gallium / drivers / r600 / r600_resource.h

diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index dd0b613485c086f4bb3bf4e141d8530ee923add8..92b9cc50b98088495f0f1f7d833d3082bc3de9ac 100644 (file)
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -23,11 +23,15 @@
 #ifndef R600_RESOURCE_H
 #define R600_RESOURCE_H
 
-#include "r600.h"
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+#include "../radeon/r600_pipe_common.h"
+
+struct r600_screen;
 
 /* flag to indicate a resource is to be used as a transfer so should not be tiled */
 #define R600_RESOURCE_FLAG_TRANSFER            PIPE_RESOURCE_FLAG_DRV_PRIV
 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH       (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+#define R600_RESOURCE_FLAG_FORCE_TILING                (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
 
 struct r600_transfer {
        struct pipe_transfer            transfer;
@@ -59,11 +63,15 @@ struct r600_texture {
        /* FMASK and CMASK can only be used with MSAA textures for now.
         * MSAA textures cannot have mipmaps. */
        unsigned                        fmask_offset, fmask_size, fmask_bank_height;
-       unsigned                        cmask_offset, cmask_size, cmask_slice_tile_max;
+       unsigned                        fmask_slice_tile_max;
+       unsigned                        cmask_offset, cmask_size;
+       unsigned                        cmask_slice_tile_max;
 
        struct r600_resource            *htile;
        /* use htile only for first level */
        float                           depth_clear;
+
+       unsigned                        color_clear_value[2];
 };
 
 #define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
@@ -72,6 +80,7 @@ struct r600_fmask_info {
        unsigned size;
        unsigned alignment;
        unsigned bank_height;
+       unsigned slice_tile_max;
 };
 
 struct r600_cmask_info {
@@ -149,11 +158,6 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
                                                const struct pipe_resource *base,
                                                struct winsys_handle *whandle);
 
-static INLINE struct r600_resource *r600_resource(struct pipe_resource *r)
-{
-       return (struct r600_resource*)r;
-}
-
 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
                                     struct pipe_resource *texture,
                                     struct r600_texture **staging);