struct radeon_ws_bo *bo;
u32 domain;
u32 flink;
- struct pb_buffer *pb;
u32 size;
};
unsigned long pitch_override;
unsigned long bpt;
unsigned long size;
- unsigned tilled;
+ unsigned tiled;
unsigned array_mode;
unsigned tile_type;
unsigned depth;
unsigned dirty;
- struct radeon_ws_bo *uncompressed;
- struct radeon_state scissor[PIPE_MAX_TEXTURE_LEVELS];
- struct radeon_state cb[8][PIPE_MAX_TEXTURE_LEVELS];
- struct radeon_state db[PIPE_MAX_TEXTURE_LEVELS];
- struct radeon_state viewport[PIPE_MAX_TEXTURE_LEVELS];
+ struct r600_resource_texture *flushed_depth_texture;
};
void r600_init_context_resource_functions(struct r600_context *r600);
-void r600_init_screen_resource_functions(struct r600_screen *r600screen);
+void r600_init_screen_resource_functions(struct pipe_screen *screen);
/* r600_buffer */
u32 r600_domain_from_usage(unsigned usage);
const struct pipe_resource *base,
struct winsys_handle *whandle);
+#define R600_BUFFER_MAGIC 0xabcd1600
+#define R600_BUFFER_MAX_RANGES 32
+
+struct r600_buffer_range {
+ uint32_t start;
+ uint32_t end;
+};
+
+struct r600_resource_buffer {
+ struct r600_resource r;
+ uint32_t magic;
+ void *user_buffer;
+ struct r600_buffer_range ranges[R600_BUFFER_MAX_RANGES];
+ unsigned num_ranges;
+};
+
+/* r600_buffer */
+static INLINE struct r600_resource_buffer *r600_buffer(struct pipe_resource *buffer)
+{
+ if (buffer) {
+ assert(((struct r600_resource_buffer *)buffer)->magic == R600_BUFFER_MAGIC);
+ return (struct r600_resource_buffer *)buffer;
+ }
+ return NULL;
+}
+
+static INLINE boolean r600_buffer_is_user_buffer(struct pipe_resource *buffer)
+{
+ return r600_buffer(buffer)->user_buffer ? TRUE : FALSE;
+}
+
+int r600_texture_depth_flush(struct pipe_context *ctx,
+ struct pipe_resource *texture);
#endif