r600g: atomize stencil ref state

[mesa.git] / src / gallium / drivers / r600 / r600_shader.c

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index e4818a082124459f54f3eca4febd97d9d1567c7b..3e797645ed9ad53c691af82e41f1c614c16df6e9 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -293,6 +293,7 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 {
        unsigned src_idx;
        unsigned inst0, inst1;
+       unsigned push_modifier;
        struct r600_bytecode_alu alu;
        memset(&alu, 0, sizeof(alu));
        for(src_idx = 0; src_idx < 3; src_idx++) {
@@ -310,12 +311,32 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
        alu.inst = inst0 | (inst1 << 8);
        alu.last = bytes[bytes_read++];
        alu.is_op3 = bytes[bytes_read++];
-       alu.predicate = bytes[bytes_read++];
+       push_modifier = bytes[bytes_read++];
+       alu.pred_sel = bytes[bytes_read++];
        alu.bank_swizzle = bytes[bytes_read++];
        alu.bank_swizzle_force = bytes[bytes_read++];
        alu.omod = bytes[bytes_read++];
        alu.index_mode = bytes[bytes_read++];
-       r600_bytecode_add_alu(ctx->bc, &alu);
+
+
+       if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE) ||
+           alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE) ||
+           alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT) ||
+           alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT)) {
+               alu.update_pred = 1;
+               alu.dst.write = 0;
+               alu.src[1].sel = V_SQ_ALU_SRC_0;
+               alu.src[1].chan = 0;
+               alu.last = 1;
+    }
+
+    if (push_modifier) {
+        alu.pred_sel = 0;
+               alu.execute_mask = 1;
+               r600_bytecode_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
+       } else
+               r600_bytecode_add_alu(ctx->bc, &alu);
+
 
        /* XXX: Handle other KILL instructions */
        if (alu.inst == CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT)) {
@@ -329,15 +350,6 @@ static unsigned r600_alu_from_byte_stream(struct r600_shader_ctx *ctx,
 static void llvm_if(struct r600_shader_ctx *ctx, struct r600_bytecode_alu * alu,
        unsigned pred_inst)
 {
-       alu->inst = pred_inst; 
-       alu->predicate = 1;
-       alu->dst.write = 0;
-       alu->src[1].sel = V_SQ_ALU_SRC_0;
-       alu->src[1].chan = 0;
-       alu->last = 1;
-       r600_bytecode_add_alu_type(ctx->bc, alu,
-               CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
-
        r600_bytecode_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
        fc_pushlevel(ctx, FC_IF);
        callstack_check_depth(ctx, FC_PUSH_VPM, 0);
@@ -3745,9 +3757,10 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
        int opcode;
        /* Texture fetch instructions can only use gprs as source.
         * Also they cannot negate the source or take the absolute value */
-       const boolean src_requires_loading = tgsi_tex_src_requires_loading(ctx, 0);
+       const boolean src_requires_loading = inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
+                                             tgsi_tex_src_requires_loading(ctx, 0);
        boolean src_loaded = FALSE;
-       unsigned sampler_src_reg = 1;
+       unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
        uint8_t offset_x = 0, offset_y = 0, offset_z = 0;
 
        src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
@@ -3880,7 +3893,8 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
        if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
             inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) &&
-           inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
+           inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
+           inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
 
                static const unsigned src0_swizzle[] = {2, 2, 0, 1};
                static const unsigned src1_swizzle[] = {1, 0, 2, 2};
@@ -4049,7 +4063,13 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
        tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
        tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
        tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
-       if (src_loaded) {
+
+       if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
+               tex.src_sel_x = 4;
+               tex.src_sel_y = 4;
+               tex.src_sel_z = 4;
+               tex.src_sel_w = 4;
+       } else if (src_loaded) {
                tex.src_sel_x = 0;
                tex.src_sel_y = 1;
                tex.src_sel_z = 2;
@@ -4846,7 +4866,8 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 
        memset(&alu, 0, sizeof(struct r600_bytecode_alu));
        alu.inst = opcode;
-       alu.predicate = 1;
+       alu.execute_mask = 1;
+       alu.update_pred = 1;
 
        alu.dst.sel = ctx->temp_reg;
        alu.dst.write = 1;
@@ -4960,7 +4981,7 @@ static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
 {
        struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
 
-       sp->mid = (struct r600_bytecode_cf **)realloc((void *)sp->mid,
+       sp->mid = realloc((void *)sp->mid,
                                                sizeof(struct r600_bytecode_cf *) * (sp->num_mid + 1));
        sp->mid[sp->num_mid] = ctx->bc->cf_last;
        sp->num_mid++;
@@ -4976,10 +4997,8 @@ static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
 static void fc_poplevel(struct r600_shader_ctx *ctx)
 {
        struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
-       if (sp->mid) {
-               free(sp->mid);
-               sp->mid = NULL;
-       }
+       free(sp->mid);
+       sp->mid = NULL;
        sp->num_mid = 0;
        sp->start = NULL;
        sp->type = 0;
@@ -5308,8 +5327,8 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_BGNSUB,    0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ENDLOOP,   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
        {TGSI_OPCODE_ENDSUB,    0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TXQ_LZ,    0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
        /* gap */
-       {103,                   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {104,                   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {105,                   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {106,                   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -5335,7 +5354,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_ISGE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE_INT, tgsi_op2},
        {TGSI_OPCODE_ISHR,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT, tgsi_op2_trans},
        {TGSI_OPCODE_ISLT,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT_INT, tgsi_op2_swap},
-       {TGSI_OPCODE_F2U,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2},
+       {TGSI_OPCODE_F2U,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_UINT, tgsi_op2_trans},
        {TGSI_OPCODE_U2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_UINT_TO_FLT, tgsi_op2_trans},
        {TGSI_OPCODE_UADD,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT, tgsi_op2},
        {TGSI_OPCODE_UDIV,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_udiv},
@@ -5482,8 +5501,8 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_BGNSUB,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ENDLOOP,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
        {TGSI_OPCODE_ENDSUB,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TXQ_LZ,    0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
        /* gap */
-       {103,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {104,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {105,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {106,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -5656,8 +5675,8 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_BGNSUB,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ENDLOOP,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
        {TGSI_OPCODE_ENDSUB,    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_TXQ_LZ,    0, SQ_TEX_INST_GET_TEXTURE_RESINFO, tgsi_tex},
        /* gap */
-       {103,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {104,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {105,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {106,                   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},