vc4: Add support for 16-bit signed/unsigned norm/scaled vertex attrs.

[mesa.git] / src / gallium / drivers / r600 / r600_shader.c

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 5135f18da204910c71a31a117253cfc27b762c17..471df91d8f38c7af1eb4602e0e6488142a6b245f 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -5035,8 +5035,9 @@ static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
        alu.op = ALU_OP1_MOV;
 
        if (ctx->bc->chip_class >= EVERGREEN) {
-               alu.src[0].sel = 512 + (id / 4);
-               alu.src[0].chan = id % 4;
+               /* channel 0 or 2 of each word */
+               alu.src[0].sel = 512 + (id / 2);
+               alu.src[0].chan = (id % 2) * 2;
        } else {
                /* r600 we have them at channel 2 of the second dword */
                alu.src[0].sel = 512 + (id * 2) + 1;
@@ -5697,9 +5698,16 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
                memset(&alu, 0, sizeof(struct r600_bytecode_alu));
                alu.op = ALU_OP1_MOV;
 
-               alu.src[0].sel = 512 + (id / 4);
-               alu.src[0].kc_bank = R600_TXQ_CONST_BUFFER;
-               alu.src[0].chan = id % 4;
+               if (ctx->bc->chip_class >= EVERGREEN) {
+                       /* channel 1 or 3 of each word */
+                       alu.src[0].sel = 512 + (id / 2);
+                       alu.src[0].chan = ((id % 2) * 2) + 1;
+               } else {
+                       /* r600 we have them at channel 2 of the second dword */
+                       alu.src[0].sel = 512 + (id * 2) + 1;
+                       alu.src[0].chan = 2;
+               }
+               alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
                tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
                alu.last = 1;
                r = r600_bytecode_add_alu(ctx->bc, &alu);
@@ -6063,7 +6071,7 @@ static int tgsi_ucmp(struct r600_shader_ctx *ctx)
                        continue;
 
                memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-               alu.op = ALU_OP3_CNDGE_INT;
+               alu.op = ALU_OP3_CNDE_INT;
                r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
                r600_bytecode_src(&alu.src[1], &ctx->src[2], i);
                r600_bytecode_src(&alu.src[2], &ctx->src[1], i);
@@ -7207,7 +7215,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_MAD,       1, ALU_OP3_MULADD, tgsi_op3},
        {TGSI_OPCODE_SUB,       0, ALU_OP2_ADD, tgsi_op2},
        {TGSI_OPCODE_LRP,       0, ALU_OP0_NOP, tgsi_lrp},
-       {TGSI_OPCODE_CND,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {19,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SQRT,      0, ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
        {TGSI_OPCODE_DP2A,      0, ALU_OP0_NOP, tgsi_unsupported},
        {22,                    0, ALU_OP0_NOP, tgsi_unsupported},
@@ -7232,14 +7240,14 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_PK2US,     0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PK4B,      0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PK4UB,     0, ALU_OP0_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_RFL,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {44,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SEQ,       0, ALU_OP2_SETE, tgsi_op2},
-       {TGSI_OPCODE_SFL,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {46,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SGT,       0, ALU_OP2_SETGT, tgsi_op2},
        {TGSI_OPCODE_SIN,       0, ALU_OP1_SIN, tgsi_trig},
        {TGSI_OPCODE_SLE,       0, ALU_OP2_SETGE, tgsi_op2_swap},
        {TGSI_OPCODE_SNE,       0, ALU_OP2_SETNE, tgsi_op2},
-       {TGSI_OPCODE_STR,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {51,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TEX,       0, FETCH_OP_SAMPLE, tgsi_tex},
        {TGSI_OPCODE_TXD,       0, FETCH_OP_SAMPLE_G, tgsi_tex},
        {TGSI_OPCODE_TXP,       0, FETCH_OP_SAMPLE, tgsi_tex},
@@ -7247,10 +7255,10 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_UP2US,     0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_UP4B,      0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_UP4UB,     0, ALU_OP0_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_X2D,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {59,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {60,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ARR,       0, ALU_OP0_NOP, tgsi_r600_arl},
-       {TGSI_OPCODE_BRA,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {62,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CAL,       0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_RET,       0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SSG,       0, ALU_OP0_NOP, tgsi_ssg},
@@ -7406,7 +7414,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_MAD,       1, ALU_OP3_MULADD, tgsi_op3},
        {TGSI_OPCODE_SUB,       0, ALU_OP2_ADD, tgsi_op2},
        {TGSI_OPCODE_LRP,       0, ALU_OP0_NOP, tgsi_lrp},
-       {TGSI_OPCODE_CND,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {19,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SQRT,      0, ALU_OP1_SQRT_IEEE, tgsi_trans_srcx_replicate},
        {TGSI_OPCODE_DP2A,      0, ALU_OP0_NOP, tgsi_unsupported},
        {22,                    0, ALU_OP0_NOP, tgsi_unsupported},
@@ -7431,14 +7439,14 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_PK2US,     0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PK4B,      0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PK4UB,     0, ALU_OP0_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_RFL,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {44,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SEQ,       0, ALU_OP2_SETE, tgsi_op2},
-       {TGSI_OPCODE_SFL,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {46,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SGT,       0, ALU_OP2_SETGT, tgsi_op2},
        {TGSI_OPCODE_SIN,       0, ALU_OP1_SIN, tgsi_trig},
        {TGSI_OPCODE_SLE,       0, ALU_OP2_SETGE, tgsi_op2_swap},
        {TGSI_OPCODE_SNE,       0, ALU_OP2_SETNE, tgsi_op2},
-       {TGSI_OPCODE_STR,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {51,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TEX,       0, FETCH_OP_SAMPLE, tgsi_tex},
        {TGSI_OPCODE_TXD,       0, FETCH_OP_SAMPLE_G, tgsi_tex},
        {TGSI_OPCODE_TXP,       0, FETCH_OP_SAMPLE, tgsi_tex},
@@ -7446,10 +7454,10 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_UP2US,     0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_UP4B,      0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_UP4UB,     0, ALU_OP0_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_X2D,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {59,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {60,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ARR,       0, ALU_OP0_NOP, tgsi_eg_arl},
-       {TGSI_OPCODE_BRA,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {62,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CAL,       0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_RET,       0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SSG,       0, ALU_OP0_NOP, tgsi_ssg},
@@ -7605,7 +7613,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_MAD,       1, ALU_OP3_MULADD, tgsi_op3},
        {TGSI_OPCODE_SUB,       0, ALU_OP2_ADD, tgsi_op2},
        {TGSI_OPCODE_LRP,       0, ALU_OP0_NOP, tgsi_lrp},
-       {TGSI_OPCODE_CND,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {19,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SQRT,      0, ALU_OP1_SQRT_IEEE, cayman_emit_float_instr},
        {TGSI_OPCODE_DP2A,      0, ALU_OP0_NOP, tgsi_unsupported},
        {22,                    0, ALU_OP0_NOP, tgsi_unsupported},
@@ -7630,14 +7638,14 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_PK2US,     0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PK4B,      0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PK4UB,     0, ALU_OP0_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_RFL,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {44,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SEQ,       0, ALU_OP2_SETE, tgsi_op2},
-       {TGSI_OPCODE_SFL,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {46,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SGT,       0, ALU_OP2_SETGT, tgsi_op2},
        {TGSI_OPCODE_SIN,       0, ALU_OP1_SIN, cayman_trig},
        {TGSI_OPCODE_SLE,       0, ALU_OP2_SETGE, tgsi_op2_swap},
        {TGSI_OPCODE_SNE,       0, ALU_OP2_SETNE, tgsi_op2},
-       {TGSI_OPCODE_STR,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {51,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_TEX,       0, FETCH_OP_SAMPLE, tgsi_tex},
        {TGSI_OPCODE_TXD,       0, FETCH_OP_SAMPLE_G, tgsi_tex},
        {TGSI_OPCODE_TXP,       0, FETCH_OP_SAMPLE, tgsi_tex},
@@ -7645,10 +7653,10 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_UP2US,     0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_UP4B,      0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_UP4UB,     0, ALU_OP0_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_X2D,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {59,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {60,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ARR,       0, ALU_OP0_NOP, tgsi_eg_arl},
-       {TGSI_OPCODE_BRA,       0, ALU_OP0_NOP, tgsi_unsupported},
+       {62,                    0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_CAL,       0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_RET,       0, ALU_OP0_NOP, tgsi_unsupported},
        {TGSI_OPCODE_SSG,       0, ALU_OP0_NOP, tgsi_ssg},