}
use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL);
use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL);
+ use_sb &= (shader->shader.processor_type != PIPE_SHADER_COMPUTE);
/* disable SB for shaders using doubles */
use_sb &= !shader->shader.uses_doubles;
use_sb &= !shader->shader.uses_atomics;
use_sb &= !shader->shader.uses_images;
+ use_sb &= !shader->shader.uses_helper_invocation;
/* Check if the bytecode has already been built. */
if (!shader->shader.bc.bytecode) {
r600_update_ps_state(ctx, shader);
}
break;
+ case PIPE_SHADER_COMPUTE:
+ evergreen_update_ls_state(ctx, shader);
+ break;
default:
r = -EINVAL;
goto error;
boolean clip_vertex_write;
unsigned cv_output;
unsigned edgeflag_output;
+ int helper_invoc_reg;
+ int cs_block_size_reg;
+ int cs_grid_size_reg;
+ bool cs_block_size_loaded, cs_grid_size_loaded;
int fragcoord_input;
- int native_integers;
int next_ring_offset;
int gs_out_ring_offset;
int gs_next_vertex;
unsigned tess_input_info; /* temp with tess input offsets */
unsigned tess_output_info; /* temp with tess input offsets */
unsigned thread_id_gpr; /* temp with thread id calculated for images */
+ bool thread_id_gpr_loaded;
};
struct r600_shader_tgsi_instruction {
int r;
/* validate this for other ops */
- assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT);
+ assert(op == ALU_OP3_MULADD_UINT24 || op == ALU_OP3_CNDE_INT || op == ALU_OP3_BFE_UINT);
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = op;
alu.src[0].sel = src0_sel;
case TGSI_FILE_ADDRESS:
case TGSI_FILE_BUFFER:
case TGSI_FILE_IMAGE:
+ case TGSI_FILE_MEMORY:
break;
case TGSI_FILE_HW_ATOMIC:
d->Semantic.Name == TGSI_SEMANTIC_SAMPLEPOS) {
break; /* Already handled from allocate_system_value_inputs */
} else if (d->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
- if (!ctx->native_integers) {
- struct r600_bytecode_alu alu;
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-
- alu.op = ALU_OP1_INT_TO_FLT;
- alu.src[0].sel = 0;
- alu.src[0].chan = 3;
-
- alu.dst.sel = 0;
- alu.dst.chan = 3;
- alu.dst.write = 1;
- alu.last = 1;
-
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
break;
} else if (d->Semantic.Name == TGSI_SEMANTIC_VERTEXID)
break;
if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
location = TGSI_INTERPOLATE_LOC_CENTER;
- inputs[1].enabled = true; /* needs SAMPLEID */
} else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
location = TGSI_INTERPOLATE_LOC_CENTER;
/* Needs sample positions, currently those are always available */
tgsi_parse_free(&parse);
+ if (ctx->info.reads_samplemask &&
+ (ctx->info.uses_linear_sample || ctx->info.uses_linear_sample)) {
+ inputs[1].enabled = true;
+ }
+
+ if (ctx->bc->chip_class >= EVERGREEN) {
+ int num_baryc = 0;
+ /* assign gpr to each interpolator according to priority */
+ for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
+ if (ctx->eg_interpolators[i].enabled) {
+ ctx->eg_interpolators[i].ij_index = num_baryc;
+ num_baryc++;
+ }
+ }
+ num_baryc = (num_baryc + 1) >> 1;
+ gpr_offset += num_baryc;
+ }
+
for (i = 0; i < ARRAY_SIZE(inputs); i++) {
boolean enabled = inputs[i].enabled;
int *reg = inputs[i].reg;
* for evergreen we need to scan the shader to find the number of GPRs we need to
* reserve for interpolation and system values
*
- * we need to know if we are going to emit
- * any sample or centroid inputs
+ * we need to know if we are going to emit any sample or centroid inputs
* if perspective and linear are required
*/
static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
{
unsigned i;
- int num_baryc;
- struct tgsi_parse_context parse;
memset(&ctx->eg_interpolators, 0, sizeof(ctx->eg_interpolators));
+ /*
+ * Could get this information from the shader info. But right now
+ * we interpolate all declared inputs, whereas the shader info will
+ * only contain the bits if the inputs are actually used, so it might
+ * not be safe...
+ */
for (i = 0; i < ctx->info.num_inputs; i++) {
int k;
/* skip position/face/mask/sampleid */
ctx->eg_interpolators[k].enabled = TRUE;
}
- if (tgsi_parse_init(&parse, ctx->tokens) != TGSI_PARSE_OK) {
- return 0;
- }
-
- /* need to scan shader for system values and interpolateAtSample/Offset/Centroid */
- while (!tgsi_parse_end_of_tokens(&parse)) {
- tgsi_parse_token(&parse);
-
- if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION) {
- const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
- if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
- inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
- inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
- {
- int interpolate, location, k;
-
- if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
- location = TGSI_INTERPOLATE_LOC_CENTER;
- } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
- location = TGSI_INTERPOLATE_LOC_CENTER;
- } else {
- location = TGSI_INTERPOLATE_LOC_CENTROID;
- }
-
- interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
- k = eg_get_interpolator_index(interpolate, location);
- if (k >= 0)
- ctx->eg_interpolators[k].enabled = true;
- }
- }
- }
-
- tgsi_parse_free(&parse);
-
- /* assign gpr to each interpolator according to priority */
- num_baryc = 0;
- for (i = 0; i < ARRAY_SIZE(ctx->eg_interpolators); i++) {
- if (ctx->eg_interpolators[i].enabled) {
- ctx->eg_interpolators[i].ij_index = num_baryc;
- num_baryc ++;
- }
- }
-
/* XXX PULL MODEL and LINE STIPPLE */
- num_baryc = (num_baryc + 1) >> 1;
- return allocate_system_value_inputs(ctx, num_baryc);
+ return allocate_system_value_inputs(ctx, 0);
}
/* sample_id_sel == NULL means fetch for current sample */
struct r600_bytecode_vtx vtx;
int r, t1;
- assert(ctx->fixed_pt_position_gpr != -1);
-
t1 = r600_get_temp(ctx);
memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
if (sample_id == NULL) {
+ assert(ctx->fixed_pt_position_gpr != -1);
+
vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
vtx.src_sel_x = 3;
}
vtx.num_format_all = 2;
vtx.format_comp_all = 1;
vtx.use_const_fields = 0;
- vtx.offset = 1; // first element is size of buffer
+ vtx.offset = 0;
+ vtx.endian = r600_endian_swap(32);
+ vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
+
+ r = r600_bytecode_add_vtx(ctx->bc, &vtx);
+ if (r)
+ return r;
+
+ return t1;
+}
+
+static int eg_load_helper_invocation(struct r600_shader_ctx *ctx)
+{
+ int r;
+ struct r600_bytecode_alu alu;
+
+ /* do a vtx fetch with wqm set on the vtx fetch */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->helper_invoc_reg;
+ alu.dst.chan = 0;
+ alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[0].value = 0xffffffff;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* do a vtx fetch in VPM mode */
+ struct r600_bytecode_vtx vtx;
+ memset(&vtx, 0, sizeof(vtx));
+ vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
+ vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
+ vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
+ vtx.src_gpr = 0;
+ vtx.mega_fetch_count = 16; /* no idea here really... */
+ vtx.dst_gpr = ctx->helper_invoc_reg;
+ vtx.dst_sel_x = 4;
+ vtx.dst_sel_y = 7; /* SEL_Y */
+ vtx.dst_sel_z = 7; /* SEL_Z */
+ vtx.dst_sel_w = 7; /* SEL_W */
+ vtx.data_format = FMT_32;
+ if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
+ return r;
+ ctx->bc->cf_last->vpm = 1;
+ return 0;
+}
+
+static int cm_load_helper_invocation(struct r600_shader_ctx *ctx)
+{
+ int r;
+ struct r600_bytecode_alu alu;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->helper_invoc_reg;
+ alu.dst.chan = 0;
+ alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[0].value = 0xffffffff;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->helper_invoc_reg;
+ alu.dst.chan = 0;
+ alu.src[0].sel = V_SQ_ALU_SRC_0;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu_type(ctx->bc, &alu, CF_OP_ALU_VALID_PIXEL_MODE);
+ if (r)
+ return r;
+
+ return ctx->helper_invoc_reg;
+}
+
+static int load_block_grid_size(struct r600_shader_ctx *ctx, bool load_block)
+{
+ struct r600_bytecode_vtx vtx;
+ int r, t1;
+
+ if (ctx->cs_block_size_loaded)
+ return ctx->cs_block_size_reg;
+ if (ctx->cs_grid_size_loaded)
+ return ctx->cs_grid_size_reg;
+
+ t1 = load_block ? ctx->cs_block_size_reg : ctx->cs_grid_size_reg;
+ struct r600_bytecode_alu alu;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.src[0].sel = V_SQ_ALU_SRC_0;
+ alu.dst.sel = t1;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
+ vtx.op = FETCH_OP_VFETCH;
+ vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
+ vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
+ vtx.src_gpr = t1;
+ vtx.src_sel_x = 0;
+
+ vtx.mega_fetch_count = 16;
+ vtx.dst_gpr = t1;
+ vtx.dst_sel_x = 0;
+ vtx.dst_sel_y = 1;
+ vtx.dst_sel_z = 2;
+ vtx.dst_sel_w = 7;
+ vtx.data_format = FMT_32_32_32_32;
+ vtx.num_format_all = 1;
+ vtx.format_comp_all = 0;
+ vtx.use_const_fields = 0;
+ vtx.offset = load_block ? 0 : 16; // first element is size of buffer
vtx.endian = r600_endian_swap(32);
vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
if (r)
return r;
+ if (load_block)
+ ctx->cs_block_size_loaded = true;
+ else
+ ctx->cs_grid_size_loaded = true;
return t1;
}
r600_src->swizzle[2] = 0;
r600_src->swizzle[3] = 0;
r600_src->sel = 0;
+ } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_THREAD_ID) {
+ r600_src->sel = 0;
+ } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_ID) {
+ r600_src->sel = 1;
} else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) {
r600_src->swizzle[0] = 3;
r600_src->swizzle[1] = 3;
r600_src->swizzle[1] = 3;
r600_src->swizzle[2] = 3;
r600_src->swizzle[3] = 3;
+ } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_GRID_SIZE) {
+ r600_src->sel = load_block_grid_size(ctx, false);
+ } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_BLOCK_SIZE) {
+ r600_src->sel = load_block_grid_size(ctx, true);
+ } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_HELPER_INVOCATION) {
+ r600_src->sel = ctx->helper_invoc_reg;
+ r600_src->swizzle[0] = 0;
+ r600_src->swizzle[1] = 0;
+ r600_src->swizzle[2] = 0;
+ r600_src->swizzle[3] = 0;
}
} else {
if (tgsi_src->Register.Indirect)
for (i = 0; i < so->num_outputs; i++) {
struct r600_bytecode_output output;
- if (stream != -1 && stream != so->output[i].output_buffer)
+ if (stream != -1 && stream != so->output[i].stream)
continue;
memset(&output, 0, sizeof(struct r600_bytecode_output));
}
static int r600_tess_factor_read(struct r600_shader_ctx *ctx,
- int output_idx)
+ int output_idx, int nc)
{
int param;
unsigned temp_reg = r600_get_temp(ctx);
if (r)
return r;
- r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
- temp_reg, 0,
- temp_reg, 0,
- V_SQ_ALU_SRC_LITERAL, param * 16);
- if (r)
- return r;
+ if (param) {
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, param * 16);
+ if (r)
+ return r;
+ }
- do_lds_fetch_values(ctx, temp_reg, dreg, 0xf);
+ do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
return 0;
}
return -1;
if (tessouter_idx != -1) {
- r = r600_tess_factor_read(ctx, tessouter_idx);
+ r = r600_tess_factor_read(ctx, tessouter_idx, outer_comps);
if (r)
return r;
}
if (tessinner_idx != -1) {
- r = r600_tess_factor_read(ctx, tessinner_idx);
+ r = r600_tess_factor_read(ctx, tessinner_idx, inner_comps);
if (r)
return r;
}
struct r600_bytecode_alu alu;
int r;
+ if (ctx->thread_id_gpr_loaded)
+ return 0;
+
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
alu.dst.sel = ctx->temp_reg;
ctx->temp_reg, 0);
if (r)
return r;
+ ctx->thread_id_gpr_loaded = true;
return 0;
}
ctx.bc = &shader->bc;
ctx.shader = shader;
- ctx.native_integers = true;
r600_bytecode_init(ctx.bc, rscreen->b.chip_class, rscreen->b.family,
rscreen->has_compressed_msaa_texturing);
tgsi_scan_shader(tokens, &ctx.info);
shader->indirect_files = ctx.info.indirect_files;
+ shader->uses_helper_invocation = false;
shader->uses_doubles = ctx.info.uses_doubles;
shader->uses_atomics = ctx.info.file_mask[TGSI_FILE_HW_ATOMIC];
shader->nsys_inputs = 0;
shader->rat_base = key.ps.nr_cbufs;
shader->image_size_const_offset = key.ps.image_size_const_offset;
break;
+ case PIPE_SHADER_COMPUTE:
+ shader->rat_base = 0;
+ shader->image_size_const_offset = ctx.info.file_count[TGSI_FILE_SAMPLER];
+ break;
default:
break;
}
ctx.fragcoord_input = -1;
ctx.colors_used = 0;
ctx.clip_vertex_write = 0;
+ ctx.thread_id_gpr_loaded = false;
+
+ ctx.helper_invoc_reg = -1;
+ ctx.cs_block_size_reg = -1;
+ ctx.cs_grid_size_reg = -1;
+ ctx.cs_block_size_loaded = false;
+ ctx.cs_grid_size_loaded = false;
shader->nr_ps_color_exports = 0;
shader->nr_ps_max_color_exports = 0;
ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
else
ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]);
+
+ for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
+ if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_HELPER_INVOCATION) {
+ ctx.helper_invoc_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
+ shader->uses_helper_invocation = true;
+ }
+ }
}
if (ctx.type == PIPE_SHADER_GEOMETRY) {
/* FIXME 1 would be enough in some cases (3 or less input vertices) */
if (add_tess_inout)
ctx.file_offset[TGSI_FILE_INPUT]+=2;
}
+ if (ctx.type == PIPE_SHADER_COMPUTE) {
+ ctx.file_offset[TGSI_FILE_INPUT] = 2;
+ for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) {
+ if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_GRID_SIZE)
+ ctx.cs_grid_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
+ if (ctx.info.system_value_semantic_name[i] == TGSI_SEMANTIC_BLOCK_SIZE)
+ ctx.cs_block_size_reg = ctx.file_offset[TGSI_FILE_INPUT]++;
+ }
+ }
ctx.file_offset[TGSI_FILE_OUTPUT] =
ctx.file_offset[TGSI_FILE_INPUT] +
ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
- ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
- ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
- ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
- ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
+
+ int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
+ ctx.info.file_max[TGSI_FILE_TEMPORARY];
+ ctx.bc->ar_reg = ++regno;
+ ctx.bc->index_reg[0] = ++regno;
+ ctx.bc->index_reg[1] = ++regno;
if (ctx.type == PIPE_SHADER_TESS_CTRL) {
- ctx.tess_input_info = ctx.bc->ar_reg + 3;
- ctx.tess_output_info = ctx.bc->ar_reg + 4;
- ctx.temp_reg = ctx.bc->ar_reg + 5;
+ ctx.tess_input_info = ++regno;
+ ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
ctx.tess_input_info = 0;
- ctx.tess_output_info = ctx.bc->ar_reg + 3;
- ctx.temp_reg = ctx.bc->ar_reg + 4;
+ ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_GEOMETRY) {
- ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
- ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
- ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
- ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
- ctx.temp_reg = ctx.bc->ar_reg + 7;
+ ctx.gs_export_gpr_tregs[0] = ++regno;
+ ctx.gs_export_gpr_tregs[1] = ++regno;
+ ctx.gs_export_gpr_tregs[2] = ++regno;
+ ctx.gs_export_gpr_tregs[3] = ++regno;
if (ctx.shader->gs_tri_strip_adj_fix) {
- ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
- ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
- ctx.temp_reg += 2;
+ ctx.gs_rotated_input[0] = ++regno;
+ ctx.gs_rotated_input[1] = ++regno;
} else {
ctx.gs_rotated_input[0] = 0;
ctx.gs_rotated_input[1] = 1;
}
- } else {
- ctx.temp_reg = ctx.bc->ar_reg + 3;
}
- if (shader->uses_images && ctx.type == PIPE_SHADER_FRAGMENT) {
- ctx.thread_id_gpr = ctx.temp_reg;
- ctx.temp_reg++;
- } else
- ctx.thread_id_gpr = 0;
+ if (shader->uses_images) {
+ ctx.thread_id_gpr = ++regno;
+ ctx.thread_id_gpr_loaded = false;
+ }
+ ctx.temp_reg = ++regno;
shader->max_arrays = 0;
shader->num_arrays = 0;
ctx.nliterals = 0;
ctx.literals = NULL;
+ ctx.max_driver_temp_used = 0;
shader->fs_write_all = ctx.info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
ctx.info.colors_written == 1;
if (shader->fs_write_all && rscreen->b.chip_class >= EVERGREEN)
shader->nr_ps_max_color_exports = 8;
+ if (ctx.shader->uses_helper_invocation) {
+ if (ctx.bc->chip_class == CAYMAN)
+ r = cm_load_helper_invocation(&ctx);
+ else
+ r = eg_load_helper_invocation(&ctx);
+ if (r)
+ return r;
+ }
+
+ /*
+ * XXX this relies on fixed_pt_position_gpr only being present when
+ * this shader should be executed per sample. Should be the case for now...
+ */
+ if (ctx.fixed_pt_position_gpr != -1 && ctx.info.reads_samplemask) {
+ /*
+ * Fix up sample mask. The hw always gives us coverage mask for
+ * the pixel. However, for per-sample shading, we need the
+ * coverage for the shader invocation only.
+ * Also, with disabled msaa, only the first bit should be set
+ * (luckily the same fixup works for both problems).
+ * For now, we can only do it if we know this shader is always
+ * executed per sample (due to usage of bits in the shader
+ * forcing per-sample execution).
+ * If the fb is not multisampled, we'd do unnecessary work but
+ * it should still be correct.
+ * It will however do nothing for sample shading according
+ * to MinSampleShading.
+ */
+ struct r600_bytecode_alu alu;
+ int tmp = r600_get_temp(&ctx);
+ assert(ctx.face_gpr != -1);
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+
+ alu.op = ALU_OP2_LSHL_INT;
+ alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[0].value = 0x1;
+ alu.src[1].sel = ctx.fixed_pt_position_gpr;
+ alu.src[1].chan = 3;
+ alu.dst.sel = tmp;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_AND_INT;
+ alu.src[0].sel = tmp;
+ alu.src[1].sel = ctx.face_gpr;
+ alu.src[1].chan = 2;
+ alu.dst.sel = ctx.face_gpr;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ alu.last = 1;
+ if ((r = r600_bytecode_add_alu(ctx.bc, &alu)))
+ return r;
+ }
+
if (ctx.fragcoord_input >= 0) {
if (ctx.bc->chip_class == CAYMAN) {
for (j = 0 ; j < 4; j++) {
}
}
- if (ctx.thread_id_gpr) {
- load_thread_id_gpr(&ctx);
- }
-
if (ctx.type == PIPE_SHADER_GEOMETRY) {
struct r600_bytecode_alu alu;
int r;
output[j].array_base = shader->output[i].sid;
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
shader->nr_ps_color_exports++;
+ shader->ps_color_export_mask |= (0xf << (shader->output[i].sid * 4));
+
+ /* If the i-th target format is set, all previous target formats must
+ * be non-zero to avoid hangs. - from radeonsi, seems to apply to eg as well.
+ */
+ if (shader->output[i].sid > 0)
+ for (unsigned x = 0; x < shader->output[i].sid; x++)
+ shader->ps_color_export_mask |= (1 << (x*4));
+
+ if (shader->output[i].sid > shader->ps_export_highest)
+ shader->ps_export_highest = shader->output[i].sid;
if (shader->fs_write_all && (rscreen->b.chip_class >= EVERGREEN)) {
for (k = 1; k < max_color_exports; k++) {
j++;
output[j].op = CF_OP_EXPORT;
output[j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
shader->nr_ps_color_exports++;
+ shader->ps_color_export_mask |= (0xf << (j * 4));
}
}
} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
output[j].op = CF_OP_EXPORT;
j++;
shader->nr_ps_color_exports++;
+ shader->ps_color_export_mask = 0xf;
}
noutput = j;
last = r600_isa_cf(ctx.bc->cf_last->op);
/* alu clause instructions don't have EOP bit, so add NOP */
- if (!last || last->flags & CF_ALU)
+ if (!last || last->flags & CF_ALU || ctx.bc->cf_last->op == CF_OP_LOOP_END || ctx.bc->cf_last->op == CF_OP_POP)
r600_bytecode_add_cfinst(ctx.bc, CF_OP_NOP);
ctx.bc->cf_last->end_of_program = 1;
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
- int i, r;
- int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+ int i, c, r;
+ int write_mask = inst->Dst[0].Register.WriteMask;
+ int temp_reg = r600_get_temp(ctx);
assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
inst->Instruction.Opcode == TGSI_OPCODE_U2D);
- for (i = 0; i <= (lasti+1)/2; i++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ctx->inst_info->op;
-
- r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
- alu.dst.sel = ctx->temp_reg;
- alu.dst.chan = i;
- alu.dst.write = 1;
- alu.last = 1;
+ for (c = 0; c < 2; c++) {
+ int dchan = c * 2;
+ if (write_mask & (0x3 << dchan)) {
+ /* split into 24-bit int and 8-bit int */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_AND_INT;
+ alu.dst.sel = temp_reg;
+ alu.dst.chan = dchan;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
+ alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[1].value = 0xffffff00;
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_AND_INT;
+ alu.dst.sel = temp_reg;
+ alu.dst.chan = dchan + 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], c);
+ alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[1].value = 0xff;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
}
- for (i = 0; i <= lasti; i++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP1_FLT32_TO_FLT64;
+ for (c = 0; c < 2; c++) {
+ int dchan = c * 2;
+ if (write_mask & (0x3 << dchan)) {
+ for (i = dchan; i <= dchan + 1; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = i == dchan ? ctx->inst_info->op : ALU_OP1_UINT_TO_FLT;
- alu.src[0].chan = i/2;
- if (i%2 == 0)
- alu.src[0].sel = ctx->temp_reg;
- else {
- alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
- alu.src[0].value = 0x0;
- }
- tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
- alu.last = i == lasti;
+ alu.src[0].sel = temp_reg;
+ alu.src[0].chan = i;
+ alu.dst.sel = temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ if (ctx->bc->chip_class == CAYMAN)
+ alu.last = i == dchan + 1;
+ else
+ alu.last = 1; /* trans only ops on evergreen */
+
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ }
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
+ for (c = 0; c < 2; c++) {
+ int dchan = c * 2;
+ if (write_mask & (0x3 << dchan)) {
+ for (i = 0; i < 4; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_FLT32_TO_FLT64;
+
+ alu.src[0].chan = dchan + (i / 2);
+ if (i == 0 || i == 2)
+ alu.src[0].sel = temp_reg;
+ else {
+ alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[0].value = 0x0;
+ }
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.last = i == 3;
+ alu.dst.write = 1;
+
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+
+ for (i = 0; i <= 1; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_ADD_64;
+
+ alu.src[0].chan = fp64_switch(i);
+ alu.src[0].sel = ctx->temp_reg;
+
+ alu.src[1].chan = fp64_switch(i + 2);
+ alu.src[1].sel = ctx->temp_reg;
+ tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
+ alu.last = i == 1;
+
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
}
return 0;
return tgsi_helper_tempx_replicate(ctx);
}
+static int emit_mul_int_op(struct r600_bytecode *bc,
+ struct r600_bytecode_alu *alu_src)
+{
+ struct r600_bytecode_alu alu;
+ int i, r;
+ alu = *alu_src;
+ if (bc->chip_class == CAYMAN) {
+ for (i = 0; i < 4; i++) {
+ alu.dst.chan = i;
+ alu.dst.write = (i == alu_src->dst.chan);
+ alu.last = (i == 3);
+
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
+ }
+ } else {
+ alu.last = 1;
+ r = r600_bytecode_add_alu(bc, &alu);
+ if (r)
+ return r;
+ }
+ return 0;
+}
+
static int tgsi_divmod(struct r600_shader_ctx *ctx, int mod, int signed_op)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
}
/* 2. tmp0.z = lo (tmp0.x * src2) */
- if (ctx->bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = j;
- alu.dst.write = (j == 2);
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULLO_UINT;
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 0;
- if (signed_op) {
- alu.src[1].sel = tmp2;
- alu.src[1].chan = 1;
- } else {
- r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
- }
+ alu.dst.sel = tmp0;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
- alu.last = (j == 3);
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
+ alu.src[0].sel = tmp0;
+ alu.src[0].chan = 0;
+ if (signed_op) {
+ alu.src[1].sel = tmp2;
+ alu.src[1].chan = 1;
} else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = 2;
- alu.dst.write = 1;
-
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 0;
- if (signed_op) {
- alu.src[1].sel = tmp2;
- alu.src[1].chan = 1;
- } else {
- r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
- }
-
- alu.last = 1;
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
}
+ if ((r = emit_mul_int_op(ctx->bc, &alu)))
+ return r;
+
/* 3. tmp0.w = -tmp0.z */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP2_SUB_INT;
return r;
/* 4. tmp0.y = hi (tmp0.x * src2) */
- if (ctx->bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULHI_UINT;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULHI_UINT;
- alu.dst.sel = tmp0;
- alu.dst.chan = j;
- alu.dst.write = (j == 1);
+ alu.dst.sel = tmp0;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 0;
+ alu.src[0].sel = tmp0;
+ alu.src[0].chan = 0;
- if (signed_op) {
- alu.src[1].sel = tmp2;
- alu.src[1].chan = 1;
- } else {
- r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
- }
- alu.last = (j == 3);
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
+ if (signed_op) {
+ alu.src[1].sel = tmp2;
+ alu.src[1].chan = 1;
} else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULHI_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = 1;
- alu.dst.write = 1;
-
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 0;
-
- if (signed_op) {
- alu.src[1].sel = tmp2;
- alu.src[1].chan = 1;
- } else {
- r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
- }
-
- alu.last = 1;
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
}
+ if ((r = emit_mul_int_op(ctx->bc, &alu)))
+ return r;
+
/* 5. tmp0.z = (tmp0.y == 0 ? tmp0.w : tmp0.z) = abs(lo(rcp*src)) */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_CNDE_INT;
return r;
/* 6. tmp0.w = hi (tmp0.z * tmp0.x) = e, rounding error */
- if (ctx->bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULHI_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = j;
- alu.dst.write = (j == 3);
-
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 2;
-
- alu.src[1].sel = tmp0;
- alu.src[1].chan = 0;
-
- alu.last = (j == 3);
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
- } else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULHI_UINT;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULHI_UINT;
- alu.dst.sel = tmp0;
- alu.dst.chan = 3;
- alu.dst.write = 1;
+ alu.dst.sel = tmp0;
+ alu.dst.chan = 3;
+ alu.dst.write = 1;
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 2;
+ alu.src[0].sel = tmp0;
+ alu.src[0].chan = 2;
- alu.src[1].sel = tmp0;
- alu.src[1].chan = 0;
+ alu.src[1].sel = tmp0;
+ alu.src[1].chan = 0;
- alu.last = 1;
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
+ if ((r = emit_mul_int_op(ctx->bc, &alu)))
return r;
- }
/* 7. tmp1.x = tmp0.x - tmp0.w */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
return r;
/* 10. tmp0.z = hi(tmp0.x * src1) = q */
- if (ctx->bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULHI_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = j;
- alu.dst.write = (j == 2);
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULHI_UINT;
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 0;
+ alu.dst.sel = tmp0;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
- if (signed_op) {
- alu.src[1].sel = tmp2;
- alu.src[1].chan = 0;
- } else {
- r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
- }
+ alu.src[0].sel = tmp0;
+ alu.src[0].chan = 0;
- alu.last = (j == 3);
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
+ if (signed_op) {
+ alu.src[1].sel = tmp2;
+ alu.src[1].chan = 0;
} else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULHI_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = 2;
- alu.dst.write = 1;
-
- alu.src[0].sel = tmp0;
- alu.src[0].chan = 0;
-
- if (signed_op) {
- alu.src[1].sel = tmp2;
- alu.src[1].chan = 0;
- } else {
- r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
- }
-
- alu.last = 1;
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
+ r600_bytecode_src(&alu.src[1], &ctx->src[0], i);
}
- /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
- if (ctx->bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = j;
- alu.dst.write = (j == 1);
+ if ((r = emit_mul_int_op(ctx->bc, &alu)))
+ return r;
- if (signed_op) {
- alu.src[0].sel = tmp2;
- alu.src[0].chan = 1;
- } else {
- r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
- }
+ /* 11. tmp0.y = lo (src2 * tmp0.z) = src2*q = src1 - r */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULLO_UINT;
- alu.src[1].sel = tmp0;
- alu.src[1].chan = 2;
+ alu.dst.sel = tmp0;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
- alu.last = (j == 3);
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
+ if (signed_op) {
+ alu.src[0].sel = tmp2;
+ alu.src[0].chan = 1;
} else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_UINT;
-
- alu.dst.sel = tmp0;
- alu.dst.chan = 1;
- alu.dst.write = 1;
-
- if (signed_op) {
- alu.src[0].sel = tmp2;
- alu.src[0].chan = 1;
- } else {
- r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
- }
+ r600_bytecode_src(&alu.src[0], &ctx->src[1], i);
+ }
- alu.src[1].sel = tmp0;
- alu.src[1].chan = 2;
+ alu.src[1].sel = tmp0;
+ alu.src[1].chan = 2;
- alu.last = 1;
- if ((r = r600_bytecode_add_alu(ctx->bc, &alu)))
- return r;
- }
+ if ((r = emit_mul_int_op(ctx->bc, &alu)))
+ return r;
/* 12. tmp0.w = src1 - tmp0.y = r */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
int src_gpr, r, i;
int id = tgsi_tex_get_src_gpr(ctx, 1);
+ int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
if (src_requires_loading) {
vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
vtx.use_const_fields = 1;
+ vtx.buffer_index_mode = sampler_index_mode;
if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
return r;
return 0;
}
-static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset)
+static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int offset, int eg_buffer_base)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
- struct r600_bytecode_alu alu;
int r;
int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
+ int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP1_MOV;
- alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
- if (ctx->bc->chip_class >= EVERGREEN) {
- /* channel 0 or 2 of each word */
- alu.src[0].sel += (id / 2);
- alu.src[0].chan = (id % 2) * 2;
- } else {
+ if (ctx->bc->chip_class < EVERGREEN) {
+ struct r600_bytecode_alu alu;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
/* r600 we have them at channel 2 of the second dword */
alu.src[0].sel += (id * 2) + 1;
alu.src[0].chan = 1;
+ alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+ } else {
+ struct r600_bytecode_vtx vtx;
+ memset(&vtx, 0, sizeof(vtx));
+ vtx.op = FETCH_OP_GET_BUFFER_RESINFO;
+ vtx.buffer_id = id + eg_buffer_base;
+ vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
+ vtx.src_gpr = 0;
+ vtx.mega_fetch_count = 16; /* no idea here really... */
+ vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
+ vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
+ vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
+ vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
+ vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
+ vtx.data_format = FMT_32_32_32_32;
+ vtx.buffer_index_mode = sampler_index_mode;
+
+ if ((r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx)))
+ return r;
+ return 0;
}
- alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
- tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
- alu.last = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
- return 0;
}
+
static int tgsi_tex(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
- ctx->shader->uses_tex_buffers = true;
- return r600_do_buffer_txq(ctx, 1, 0);
+ if (ctx->bc->chip_class < EVERGREEN)
+ ctx->shader->uses_tex_buffers = true;
+ return r600_do_buffer_txq(ctx, 1, 0, R600_MAX_CONST_BUFFERS);
}
else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
if (ctx->bc->chip_class < EVERGREEN)
}
}
+ if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
+ /* Gather4 should follow the same rules as bilinear filtering, but the hardware
+ * incorrectly forces nearest filtering if the texture format is integer.
+ * The only effect it has on Gather4, which always returns 4 texels for
+ * bilinear filtering, is that the final coordinates are off by 0.5 of
+ * the texel size.
+ *
+ * The workaround is to subtract 0.5 from the unnormalized coordinates,
+ * or (0.5 / size) from the normalized coordinates.
+ */
+ if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
+ inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
+ int treg = r600_get_temp(ctx);
+
+ /* mov array and comparison oordinate to temp_reg if needed */
+ if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
+ inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
+ inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) && !src_loaded) {
+ int end = inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ? 3 : 2;
+ for (i = 2; i <= end; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.last = (i == end);
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+
+ if (inst->Texture.Texture == TGSI_TEXTURE_RECT ||
+ inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_ADD;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.last = i == 1;
+ if (src_loaded) {
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = i;
+ } else
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
+ alu.src[1].sel = V_SQ_ALU_SRC_0_5;
+ alu.src[1].neg = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ } else {
+ /* execute a TXQ */
+ memset(&tex, 0, sizeof(struct r600_bytecode_tex));
+ tex.op = FETCH_OP_GET_TEXTURE_RESINFO;
+ tex.sampler_id = tgsi_tex_get_src_gpr(ctx, sampler_src_reg);
+ tex.sampler_index_mode = sampler_index_mode;
+ tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
+ tex.resource_index_mode = sampler_index_mode;
+ tex.dst_gpr = treg;
+ tex.src_sel_x = 4;
+ tex.src_sel_y = 4;
+ tex.src_sel_z = 4;
+ tex.src_sel_w = 4;
+ tex.dst_sel_x = 0;
+ tex.dst_sel_y = 1;
+ tex.dst_sel_z = 7;
+ tex.dst_sel_w = 7;
+ r = r600_bytecode_add_tex(ctx->bc, &tex);
+ if (r)
+ return r;
+
+ /* coord.xy = -0.5 * (1.0/int_to_flt(size)) + coord.xy */
+ if (ctx->bc->chip_class == CAYMAN) {
+ /* */
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_INT_TO_FLT;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.last = (i == 1) ? 1 : 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ for (j = 0; j < 2; j++) {
+ for (i = 0; i < 3; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_RECIP_IEEE;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = j;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ if (i == 2)
+ alu.last = 1;
+ if (i == j)
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ } else {
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_INT_TO_FLT;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_RECIP_IEEE;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.dst.sel = treg;
+ alu.dst.chan = i;
+ alu.last = 1;
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ for (i = 0; i < 2; i++) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP3_MULADD;
+ alu.is_op3 = 1;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
+ alu.dst.write = 1;
+ alu.last = i == 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = i;
+ alu.src[1].sel = V_SQ_ALU_SRC_0_5;
+ alu.src[1].neg = 1;
+ if (src_loaded) {
+ alu.src[2].sel = ctx->temp_reg;
+ alu.src[2].chan = i;
+ } else
+ r600_bytecode_src(&alu.src[2], &ctx->src[0], i);
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ src_loaded = TRUE;
+ src_gpr = ctx->temp_reg;
+ }
+ }
+
if (src_requires_loading && !src_loaded) {
for (i = 0; i < 4; i++) {
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
return r;
/* temp.x = sample_index*4 */
- if (ctx->bc->chip_class == CAYMAN) {
- for (i = 0 ; i < 4; i++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_INT;
- alu.src[0].sel = src_gpr;
- alu.src[0].chan = sample_chan;
- alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
- alu.src[1].value = 4;
- alu.dst.sel = temp;
- alu.dst.chan = i;
- alu.dst.write = i == 0;
- if (i == 3)
- alu.last = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
- }
- } else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_INT;
- alu.src[0].sel = src_gpr;
- alu.src[0].chan = sample_chan;
- alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
- alu.src[1].value = 4;
- alu.dst.sel = temp;
- alu.dst.chan = 0;
- alu.dst.write = 1;
- alu.last = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
- }
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULLO_INT;
+ alu.src[0].sel = src_gpr;
+ alu.src[0].chan = sample_chan;
+ alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[1].value = 4;
+ alu.dst.sel = temp;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ r = emit_mul_int_op(ctx->bc, &alu);
+ if (r)
+ return r;
/* sample_index = temp.w >> temp.x */
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
if (ctx->bc->chip_class >= EVERGREEN) {
- /* channel 1 or 3 of each word */
- alu.src[0].sel += (id / 2);
- alu.src[0].chan = ((id % 2) * 2) + 1;
+ /* with eg each dword is number of cubes */
+ alu.src[0].sel += id / 4;
+ alu.src[0].chan = id % 4;
} else {
/* r600 we have them at channel 2 of the second dword */
alu.src[0].sel += (id * 2) + 1;
tex.inst_mod = texture_component_select;
if (ctx->bc->chip_class == CAYMAN) {
- /* GATHER4 result order is different from TGSI TG4 */
- tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 0 : 7;
- tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 1 : 7;
- tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 2 : 7;
+ tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+ tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+ tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
} else {
- tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
- tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
- tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+ /* GATHER4 result order is different from TGSI TG4 */
+ tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
+ tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
+ tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
}
}
int *uav_id_p, int *uav_index_mode_p)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
- int uav_id, uav_index_mode;
+ int uav_id, uav_index_mode = 0;
int r;
bool is_cm = (ctx->bc->chip_class == CAYMAN);
return 0;
}
-static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
+static int load_buffer_coord(struct r600_shader_ctx *ctx, int src_idx,
+ int temp_reg)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
- /* have to work out the offset into the RAT immediate return buffer */
- struct r600_bytecode_vtx vtx;
- struct r600_bytecode_cf *cf;
int r;
- int temp_reg = r600_get_temp(ctx);
- unsigned rat_index_mode;
- unsigned base;
-
- rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
- base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
-
- if (inst->Src[1].Register.File == TGSI_FILE_IMMEDIATE) {
- int value = (ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX]);
+ if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
+ int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
r = single_alu_op2(ctx, ALU_OP1_MOV,
temp_reg, 0,
V_SQ_ALU_SRC_LITERAL, value >> 2,
struct r600_bytecode_alu alu;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP2_LSHR_INT;
- r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
+ r600_bytecode_src(&alu.src[0], &ctx->src[src_idx], 0);
alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[1].value = 2;
alu.dst.sel = temp_reg;
if (r)
return r;
}
+ return 0;
+}
+
+static int tgsi_load_buffer(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ /* have to work out the offset into the RAT immediate return buffer */
+ struct r600_bytecode_vtx vtx;
+ struct r600_bytecode_cf *cf;
+ int r;
+ int temp_reg = r600_get_temp(ctx);
+ unsigned rat_index_mode;
+ unsigned base;
+
+ rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
+ base = R600_IMAGE_REAL_RESOURCE_OFFSET + ctx->info.file_count[TGSI_FILE_IMAGE];
+
+ r = load_buffer_coord(ctx, 1, temp_reg);
+ if (r)
+ return r;
ctx->bc->cf_last->barrier = 1;
memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
vtx.op = FETCH_OP_VFETCH;
vtx.format_comp_all = 1;
vtx.srf_mode_all = 0;
- if (inst->Dst[0].Register.WriteMask == 0xf) {
+ if (inst->Dst[0].Register.WriteMask & 8) {
vtx.data_format = FMT_32_32_32_32;
vtx.use_const_fields = 0;
- } else if (inst->Dst[0].Register.WriteMask == 0x7) {
+ } else if (inst->Dst[0].Register.WriteMask & 4) {
vtx.data_format = FMT_32_32_32;
vtx.use_const_fields = 0;
- } else if (inst->Dst[0].Register.WriteMask == 0x3) {
+ } else if (inst->Dst[0].Register.WriteMask & 2) {
vtx.data_format = FMT_32_32;
vtx.use_const_fields = 0;
- } else
- vtx.use_const_fields = 1;
+ } else {
+ vtx.data_format = FMT_32;
+ vtx.use_const_fields = 0;
+ }
r = r600_bytecode_add_vtx_tc(ctx->bc, &vtx);
if (r)
unsigned rat_index_mode;
unsigned immed_base;
+ r = load_thread_id_gpr(ctx);
+ if (r)
+ return r;
+
rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
return 0;
}
+static int tgsi_load_lds(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+ int temp_reg = r600_get_temp(ctx);
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
+ alu.dst.sel = temp_reg;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ r = do_lds_fetch_values(ctx, temp_reg,
+ ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
+ if (r)
+ return r;
+ return 0;
+}
+
static int tgsi_load(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
return tgsi_load_gds(ctx);
if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
return tgsi_load_buffer(ctx);
+ if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
+ return tgsi_load_lds(ctx);
return 0;
}
int lasti;
int temp_reg = r600_get_temp(ctx), treg2 = r600_get_temp(ctx);
- if (inst->Src[0].Register.File == TGSI_FILE_IMMEDIATE) {
- int value = (ctx->literals[4 * inst->Src[0].Register.Index + inst->Src[0].Register.SwizzleX]);
- r = single_alu_op2(ctx, ALU_OP1_MOV,
- treg2, 0,
- V_SQ_ALU_SRC_LITERAL, value >> 2,
- 0, 0);
- if (r)
- return r;
- } else {
- r = single_alu_op2(ctx, ALU_OP2_LSHR_INT,
- treg2, 0,
- ctx->src[0].sel, ctx->src[0].swizzle[0],
- V_SQ_ALU_SRC_LITERAL, 2);
- if (r)
- return r;
- }
+ r = load_buffer_coord(ctx, 0, treg2);
+ if (r)
+ return r;
rat_index_mode = inst->Dst[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
if (rat_index_mode)
return 0;
}
+static int tgsi_store_lds(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r, i, lasti;
+ int write_mask = inst->Dst[0].Register.WriteMask;
+ int temp_reg = r600_get_temp(ctx);
+
+ /* LDS write */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ alu.dst.sel = temp_reg;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ lasti = tgsi_last_instruction(write_mask);
+ for (i = 1; i <= lasti; i++) {
+ if (!(write_mask & (1 << i)))
+ continue;
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, i,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, 4 * i);
+ if (r)
+ return r;
+ }
+ for (i = 0; i <= lasti; i++) {
+ if (!(write_mask & (1 << i)))
+ continue;
+
+ if ((i == 0 && ((write_mask & 3) == 3)) ||
+ (i == 2 && ((write_mask & 0xc) == 0xc))) {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = LDS_OP3_LDS_WRITE_REL;
+
+ alu.src[0].sel = temp_reg;
+ alu.src[0].chan = i;
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
+ r600_bytecode_src(&alu.src[2], &ctx->src[1], i + 1);
+ alu.last = 1;
+ alu.is_lds_idx_op = true;
+ alu.lds_idx = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ i += 1;
+ continue;
+ }
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = LDS_OP2_LDS_WRITE;
+
+ alu.src[0].sel = temp_reg;
+ alu.src[0].chan = i;
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], i);
+
+ alu.last = 1;
+ alu.is_lds_idx_op = true;
+
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ return 0;
+}
+
static int tgsi_store(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
return tgsi_store_buffer_rat(ctx);
+ else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
+ return tgsi_store_lds(ctx);
else
return tgsi_store_rat(ctx);
}
immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
rat_base = ctx->shader->rat_base;
+ r = load_thread_id_gpr(ctx);
+ if (r)
+ return r;
+
if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];
+
+ r = load_buffer_coord(ctx, 1, ctx->temp_reg);
+ if (r)
+ return r;
+ idx_gpr = ctx->temp_reg;
+ } else {
+ r = load_index_src(ctx, 1, &idx_gpr);
+ if (r)
+ return r;
}
rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
- r = load_index_src(ctx, 1, &idx_gpr);
- if (r)
- return r;
-
if (ctx->inst_info->op == V_RAT_INST_CMPXCHG_INT_RTN) {
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MOV;
cf->barrier = 1;
cf->cf_addr = 1;
- desc = util_format_description(inst->Memory.Format);
- r600_vertex_data_type(inst->Memory.Format,
- &format, &num_format, &format_comp, &endian);
memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
+ if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
+ desc = util_format_description(inst->Memory.Format);
+ r600_vertex_data_type(inst->Memory.Format,
+ &format, &num_format, &format_comp, &endian);
+ vtx.dst_sel_x = desc->swizzle[0];
+ } else {
+ format = FMT_32;
+ num_format = 1;
+ format_comp = 0;
+ endian = 0;
+ vtx.dst_sel_x = 0;
+ }
vtx.op = FETCH_OP_VFETCH;
vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
vtx.buffer_index_mode = rat_index_mode;
vtx.src_gpr = ctx->thread_id_gpr;
vtx.src_sel_x = 1;
vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
- vtx.dst_sel_x = desc->swizzle[0];
vtx.dst_sel_y = 7;
vtx.dst_sel_z = 7;
vtx.dst_sel_w = 7;
if (r)
return r;
- if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
- int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
- int abs_value = abs(value);
- if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
+ if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET) {
+ if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
+ int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = is_cm ? 2 : 1;
+ alu.src[0].sel = V_SQ_ALU_SRC_LITERAL;
+ alu.src[0].value = value;
+ alu.last = 1;
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ } else {
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = is_cm ? 2 : 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[3], 0);
+ alu.last = 1;
+ alu.dst.write = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ }
+ }
+ if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
+ int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
+ int abs_value = abs(value);
+ if (abs_value != value && gds_op == FETCH_OP_GDS_ADD_RET)
gds_op = FETCH_OP_GDS_SUB_RET;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MOV;
gds.src_gpr2 = 0;
gds.src_sel_x = is_cm ? 0 : 4;
gds.src_sel_y = is_cm ? 1 : 0;
- gds.src_sel_z = 7;
+ if (gds_op == FETCH_OP_GDS_CMP_XCHG_RET)
+ gds.src_sel_z = is_cm ? 2 : 1;
+ else
+ gds.src_sel_z = 7;
gds.dst_sel_x = 0;
gds.dst_sel_y = 7;
gds.dst_sel_z = 7;
return 0;
}
+static int get_lds_op(int opcode)
+{
+ switch (opcode) {
+ case TGSI_OPCODE_ATOMUADD:
+ return LDS_OP2_LDS_ADD_RET;
+ case TGSI_OPCODE_ATOMAND:
+ return LDS_OP2_LDS_AND_RET;
+ case TGSI_OPCODE_ATOMOR:
+ return LDS_OP2_LDS_OR_RET;
+ case TGSI_OPCODE_ATOMXOR:
+ return LDS_OP2_LDS_XOR_RET;
+ case TGSI_OPCODE_ATOMUMIN:
+ return LDS_OP2_LDS_MIN_UINT_RET;
+ case TGSI_OPCODE_ATOMUMAX:
+ return LDS_OP2_LDS_MAX_UINT_RET;
+ case TGSI_OPCODE_ATOMIMIN:
+ return LDS_OP2_LDS_MIN_INT_RET;
+ case TGSI_OPCODE_ATOMIMAX:
+ return LDS_OP2_LDS_MAX_INT_RET;
+ case TGSI_OPCODE_ATOMXCHG:
+ return LDS_OP2_LDS_XCHG_RET;
+ case TGSI_OPCODE_ATOMCAS:
+ return LDS_OP3_LDS_CMP_XCHG_RET;
+ default:
+ return -1;
+ }
+}
+
+static int tgsi_atomic_op_lds(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ int lds_op = get_lds_op(inst->Instruction.Opcode);
+ int r;
+
+ struct r600_bytecode_alu alu;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = lds_op;
+ alu.is_lds_idx_op = true;
+ alu.last = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[1], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[2], 0);
+ if (lds_op == LDS_OP3_LDS_CMP_XCHG_RET)
+ r600_bytecode_src(&alu.src[2], &ctx->src[3], 0);
+ else
+ alu.src[2].sel = V_SQ_ALU_SRC_0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* then read from LDS_OQ_A_POP */
+ memset(&alu, 0, sizeof(alu));
+
+ alu.op = ALU_OP1_MOV;
+ alu.src[0].sel = EG_V_SQ_ALU_SRC_LDS_OQ_A_POP;
+ alu.src[0].chan = 0;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.dst.write = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ return 0;
+}
+
static int tgsi_atomic_op(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
return tgsi_atomic_op_gds(ctx);
if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
return tgsi_atomic_op_rat(ctx);
+ if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
+ return tgsi_atomic_op_lds(ctx);
return 0;
}
if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
(inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
- ctx->shader->uses_tex_buffers = true;
- return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset);
+ if (ctx->bc->chip_class < EVERGREEN)
+ ctx->shader->uses_tex_buffers = true;
+ unsigned eg_buffer_base = 0;
+ eg_buffer_base = R600_IMAGE_REAL_RESOURCE_OFFSET;
+ if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
+ eg_buffer_base += ctx->info.file_count[TGSI_FILE_IMAGE];
+ return r600_do_buffer_txq(ctx, 0, ctx->shader->image_size_const_offset, eg_buffer_base);
}
if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
alu.op = ALU_OP1_MOV;
alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
- /* channel 1 or 3 of each word */
- alu.src[0].sel += (id / 2);
- alu.src[0].chan = ((id % 2) * 2) + 1;
+ /* with eg each dword is either number of cubes */
+ alu.src[0].sel += id / 4;
+ alu.src[0].chan = id % 4;
alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
alu.last = 1;
return 0;
}
-static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type)
+static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type,
+ struct r600_bytecode_alu_src *src)
{
struct r600_bytecode_alu alu;
int r;
alu.dst.write = 1;
alu.dst.chan = 0;
- r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ alu.src[0] = *src;
alu.src[1].sel = V_SQ_ALU_SRC_0;
alu.src[1].chan = 0;
}
#endif
-static int emit_if(struct r600_shader_ctx *ctx, int opcode)
+static int emit_if(struct r600_shader_ctx *ctx, int opcode,
+ struct r600_bytecode_alu_src *src)
{
int alu_type = CF_OP_ALU_PUSH_BEFORE;
alu_type = CF_OP_ALU;
}
- emit_logic_pred(ctx, opcode, alu_type);
+ emit_logic_pred(ctx, opcode, alu_type, src);
r600_bytecode_add_cfinst(ctx->bc, CF_OP_JUMP);
static int tgsi_if(struct r600_shader_ctx *ctx)
{
- return emit_if(ctx, ALU_OP2_PRED_SETNE);
+ struct r600_bytecode_alu_src alu_src;
+ r600_bytecode_src(&alu_src, &ctx->src[0], 0);
+
+ return emit_if(ctx, ALU_OP2_PRED_SETNE, &alu_src);
}
static int tgsi_uif(struct r600_shader_ctx *ctx)
{
- return emit_if(ctx, ALU_OP2_PRED_SETNE_INT);
+ struct r600_bytecode_alu_src alu_src;
+ r600_bytecode_src(&alu_src, &ctx->src[0], 0);
+ return emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
}
static int tgsi_else(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
- int i, j, k, r;
+ int i, j, r;
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
/* src0 * src1 */
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
continue;
- if (ctx->bc->chip_class == CAYMAN) {
- for (j = 0 ; j < 4; j++) {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-
- alu.op = ALU_OP2_MULLO_UINT;
- for (k = 0; k < inst->Instruction.NumSrcRegs; k++) {
- r600_bytecode_src(&alu.src[k], &ctx->src[k], i);
- }
- alu.dst.chan = j;
- alu.dst.sel = ctx->temp_reg;
- alu.dst.write = (j == i);
- if (j == 3)
- alu.last = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
- }
- } else {
- memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-
- alu.dst.chan = i;
- alu.dst.sel = ctx->temp_reg;
- alu.dst.write = 1;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
- alu.op = ALU_OP2_MULLO_UINT;
- for (j = 0; j < 2; j++) {
- r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
- }
+ alu.dst.chan = i;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.write = 1;
- alu.last = 1;
- r = r600_bytecode_add_alu(ctx->bc, &alu);
- if (r)
- return r;
+ alu.op = ALU_OP2_MULLO_UINT;
+ for (j = 0; j < 2; j++) {
+ r600_bytecode_src(&alu.src[j], &ctx->src[j], i);
}
+
+ alu.last = 1;
+ r = emit_mul_int_op(ctx->bc, &alu);
+ if (r)
+ return r;
}
return 0;
}
+static int tgsi_clock(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+ alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
+static int emit_u64add(struct r600_shader_ctx *ctx, int op,
+ int treg,
+ int src0_sel, int src0_chan,
+ int src1_sel, int src1_chan)
+{
+ struct r600_bytecode_alu alu;
+ int r;
+ int opc;
+
+ if (op == ALU_OP2_ADD_INT)
+ opc = ALU_OP2_ADDC_UINT;
+ else
+ opc = ALU_OP2_SUBB_UINT;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op; ;
+ alu.dst.sel = treg;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ alu.src[0].sel = src0_sel;
+ alu.src[0].chan = src0_chan + 0;
+ alu.src[1].sel = src1_sel;
+ alu.src[1].chan = src1_chan + 0;
+ alu.src[1].neg = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op;
+ alu.dst.sel = treg;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
+ alu.src[0].sel = src0_sel;
+ alu.src[0].chan = src0_chan + 1;
+ alu.src[1].sel = src1_sel;
+ alu.src[1].chan = src1_chan + 1;
+ alu.src[1].neg = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = opc;
+ alu.dst.sel = treg;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ alu.last = 1;
+ alu.src[0].sel = src0_sel;
+ alu.src[0].chan = src0_chan + 0;
+ alu.src[1].sel = src1_sel;
+ alu.src[1].chan = src1_chan + 0;
+ alu.src[1].neg = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op;
+ alu.dst.sel = treg;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 1;
+ alu.src[1].sel = treg;
+ alu.src[1].chan = 2;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
+static int egcm_u64add(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+ int treg = ctx->temp_reg;
+ int op = ALU_OP2_ADD_INT, opc = ALU_OP2_ADDC_UINT;
+
+ if (ctx->src[1].neg) {
+ op = ALU_OP2_SUB_INT;
+ opc = ALU_OP2_SUBB_UINT;
+ }
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op; ;
+ alu.dst.sel = treg;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
+ alu.src[1].neg = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op;
+ alu.dst.sel = treg;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
+ alu.src[1].neg = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = opc ;
+ alu.dst.sel = treg;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ alu.last = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
+ alu.src[1].neg = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = op;
+ tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 1;
+ alu.src[1].sel = treg;
+ alu.src[1].chan = 2;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 0;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
+/* result.y = mul_high a, b
+ result.x = mul a,b
+ result.y += a.x * b.y + a.y * b.x;
+*/
+static int egcm_u64mul(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+ int treg = ctx->temp_reg;
+
+ /* temp.x = mul_lo a.x, b.x */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULLO_UINT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
+ r = emit_mul_int_op(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* temp.y = mul_hi a.x, b.x */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULHI_UINT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
+ r = emit_mul_int_op(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* temp.z = mul a.x, b.y */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULLO_UINT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
+ r = emit_mul_int_op(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* temp.w = mul a.y, b.x */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_MULLO_UINT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 3;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
+ r = emit_mul_int_op(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* temp.z = temp.z + temp.w */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_ADD_INT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 2;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 2;
+ alu.src[1].sel = treg;
+ alu.src[1].chan = 3;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* temp.y = temp.y + temp.z */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_ADD_INT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 1;
+ alu.src[1].sel = treg;
+ alu.src[1].chan = 2;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* dst.x = temp.x */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 0;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ /* dst.y = temp.y */
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ return 0;
+}
+
+static int emit_u64sge(struct r600_shader_ctx *ctx,
+ int treg,
+ int src0_sel, int src0_base_chan,
+ int src1_sel, int src1_base_chan)
+{
+ int r;
+ /* for 64-bit sge */
+ /* result = (src0.y > src1.y) || ((src0.y == src1.y) && src0.x >= src1.x)) */
+ r = single_alu_op2(ctx, ALU_OP2_SETGT_UINT,
+ treg, 1,
+ src0_sel, src0_base_chan + 1,
+ src1_sel, src1_base_chan + 1);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
+ treg, 0,
+ src0_sel, src0_base_chan,
+ src1_sel, src1_base_chan);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_SETE_INT,
+ treg, 2,
+ src0_sel, src0_base_chan + 1,
+ src1_sel, src1_base_chan + 1);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_AND_INT,
+ treg, 0,
+ treg, 0,
+ treg, 2);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_OR_INT,
+ treg, 0,
+ treg, 0,
+ treg, 1);
+ if (r)
+ return r;
+ return 0;
+}
+
+/* this isn't a complete div it's just enough for qbo shader to work */
+static int egcm_u64div(struct r600_shader_ctx *ctx)
+{
+ struct r600_bytecode_alu alu;
+ struct r600_bytecode_alu_src alu_num_hi, alu_num_lo, alu_denom_hi, alu_denom_lo, alu_src;
+ int r, i;
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+
+ /* make sure we are dividing my a const with 0 in the high bits */
+ if (ctx->src[1].sel != V_SQ_ALU_SRC_LITERAL)
+ return -1;
+ if (ctx->src[1].value[ctx->src[1].swizzle[1]] != 0)
+ return -1;
+ /* make sure we are doing one division */
+ if (inst->Dst[0].Register.WriteMask != 0x3)
+ return -1;
+
+ /* emit_if uses ctx->temp_reg so we can't */
+ int treg = r600_get_temp(ctx);
+ int tmp_num = r600_get_temp(ctx);
+ int sub_tmp = r600_get_temp(ctx);
+
+ /* tmp quot are tmp_num.zw */
+ r600_bytecode_src(&alu_num_lo, &ctx->src[0], 0);
+ r600_bytecode_src(&alu_num_hi, &ctx->src[0], 1);
+ r600_bytecode_src(&alu_denom_lo, &ctx->src[1], 0);
+ r600_bytecode_src(&alu_denom_hi, &ctx->src[1], 1);
+
+ /* MOV tmp_num.xy, numerator */
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ tmp_num, 0,
+ alu_num_lo.sel, alu_num_lo.chan,
+ 0, 0);
+ if (r)
+ return r;
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ tmp_num, 1,
+ alu_num_hi.sel, alu_num_hi.chan,
+ 0, 0);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ tmp_num, 2,
+ V_SQ_ALU_SRC_LITERAL, 0,
+ 0, 0);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ tmp_num, 3,
+ V_SQ_ALU_SRC_LITERAL, 0,
+ 0, 0);
+ if (r)
+ return r;
+
+ /* treg 0 is log2_denom */
+ /* normally this gets the MSB for the denom high value
+ - however we know this will always be 0 here. */
+ r = single_alu_op2(ctx,
+ ALU_OP1_MOV,
+ treg, 0,
+ V_SQ_ALU_SRC_LITERAL, 32,
+ 0, 0);
+ if (r)
+ return r;
+
+ /* normally check demon hi for 0, but we know it is already */
+ /* t0.z = num_hi >= denom_lo */
+ r = single_alu_op2(ctx,
+ ALU_OP2_SETGE_UINT,
+ treg, 1,
+ alu_num_hi.sel, alu_num_hi.chan,
+ V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
+ if (r)
+ return r;
+
+ memset(&alu_src, 0, sizeof(alu_src));
+ alu_src.sel = treg;
+ alu_src.chan = 1;
+ r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
+ if (r)
+ return r;
+
+ /* for loops in here */
+ /* get msb t0.x = msb(src[1].x) first */
+ int msb_lo = util_last_bit(alu_denom_lo.value);
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ treg, 0,
+ V_SQ_ALU_SRC_LITERAL, msb_lo,
+ 0, 0);
+ if (r)
+ return r;
+
+ /* unroll the asm here */
+ for (i = 0; i < 31; i++) {
+ r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
+ treg, 2,
+ V_SQ_ALU_SRC_LITERAL, i,
+ treg, 0);
+ if (r)
+ return r;
+
+ /* we can do this on the CPU */
+ uint32_t denom_lo_shl = alu_denom_lo.value << (31 - i);
+ /* t0.z = tmp_num.y >= t0.z */
+ r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
+ treg, 1,
+ tmp_num, 1,
+ V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_AND_INT,
+ treg, 1,
+ treg, 1,
+ treg, 2);
+ if (r)
+ return r;
+
+ memset(&alu_src, 0, sizeof(alu_src));
+ alu_src.sel = treg;
+ alu_src.chan = 1;
+ r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
+ tmp_num, 1,
+ tmp_num, 1,
+ V_SQ_ALU_SRC_LITERAL, denom_lo_shl);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_OR_INT,
+ tmp_num, 3,
+ tmp_num, 3,
+ V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
+ if (r)
+ return r;
+
+ r = tgsi_endif(ctx);
+ if (r)
+ return r;
+ }
+
+ /* log2_denom is always <= 31, so manually peel the last loop
+ * iteration.
+ */
+ r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
+ treg, 1,
+ tmp_num, 1,
+ V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
+ if (r)
+ return r;
+
+ memset(&alu_src, 0, sizeof(alu_src));
+ alu_src.sel = treg;
+ alu_src.chan = 1;
+ r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_SUB_INT,
+ tmp_num, 1,
+ tmp_num, 1,
+ V_SQ_ALU_SRC_LITERAL, alu_denom_lo.value);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_OR_INT,
+ tmp_num, 3,
+ tmp_num, 3,
+ V_SQ_ALU_SRC_LITERAL, 1U);
+ if (r)
+ return r;
+ r = tgsi_endif(ctx);
+ if (r)
+ return r;
+
+ r = tgsi_endif(ctx);
+ if (r)
+ return r;
+
+ /* onto the second loop to unroll */
+ for (i = 0; i < 31; i++) {
+ r = single_alu_op2(ctx, ALU_OP2_SETGE_UINT,
+ treg, 1,
+ V_SQ_ALU_SRC_LITERAL, (63 - (31 - i)),
+ treg, 0);
+ if (r)
+ return r;
+
+ uint64_t denom_shl = (uint64_t)alu_denom_lo.value << (31 - i);
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ treg, 2,
+ V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
+ 0, 0);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ treg, 3,
+ V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
+ 0, 0);
+ if (r)
+ return r;
+
+ r = emit_u64sge(ctx, sub_tmp,
+ tmp_num, 0,
+ treg, 2);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_AND_INT,
+ treg, 1,
+ treg, 1,
+ sub_tmp, 0);
+ if (r)
+ return r;
+
+ memset(&alu_src, 0, sizeof(alu_src));
+ alu_src.sel = treg;
+ alu_src.chan = 1;
+ r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
+ if (r)
+ return r;
+
+
+ r = emit_u64add(ctx, ALU_OP2_SUB_INT,
+ sub_tmp,
+ tmp_num, 0,
+ treg, 2);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ tmp_num, 0,
+ sub_tmp, 0,
+ 0, 0);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ tmp_num, 1,
+ sub_tmp, 1,
+ 0, 0);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_OR_INT,
+ tmp_num, 2,
+ tmp_num, 2,
+ V_SQ_ALU_SRC_LITERAL, 1U << (31 - i));
+ if (r)
+ return r;
+
+ r = tgsi_endif(ctx);
+ if (r)
+ return r;
+ }
+
+ /* log2_denom is always <= 63, so manually peel the last loop
+ * iteration.
+ */
+ uint64_t denom_shl = (uint64_t)alu_denom_lo.value;
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ treg, 2,
+ V_SQ_ALU_SRC_LITERAL, (denom_shl & 0xffffffff),
+ 0, 0);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP1_MOV,
+ treg, 3,
+ V_SQ_ALU_SRC_LITERAL, (denom_shl >> 32),
+ 0, 0);
+ if (r)
+ return r;
+
+ r = emit_u64sge(ctx, sub_tmp,
+ tmp_num, 0,
+ treg, 2);
+ if (r)
+ return r;
+
+ memset(&alu_src, 0, sizeof(alu_src));
+ alu_src.sel = sub_tmp;
+ alu_src.chan = 0;
+ r = emit_if(ctx, ALU_OP2_PRED_SETNE_INT, &alu_src);
+ if (r)
+ return r;
+
+ r = emit_u64add(ctx, ALU_OP2_SUB_INT,
+ sub_tmp,
+ tmp_num, 0,
+ treg, 2);
+ if (r)
+ return r;
+
+ r = single_alu_op2(ctx, ALU_OP2_OR_INT,
+ tmp_num, 2,
+ tmp_num, 2,
+ V_SQ_ALU_SRC_LITERAL, 1U);
+ if (r)
+ return r;
+ r = tgsi_endif(ctx);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.src[0].sel = tmp_num;
+ alu.src[0].chan = 2;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+ alu.src[0].sel = tmp_num;
+ alu.src[0].chan = 3;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
+static int egcm_u64sne(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+ int treg = ctx->temp_reg;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_SETNE_INT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 0);
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_SETNE_INT;
+ alu.dst.sel = treg;
+ alu.dst.chan = 1;
+ alu.dst.write = 1;
+ r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
+ r600_bytecode_src(&alu.src[1], &ctx->src[1], 1);
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP2_OR_INT;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.src[0].sel = treg;
+ alu.src[0].chan = 0;
+ alu.src[1].sel = treg;
+ alu.src[1].chan = 1;
+ alu.last = 1;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
[TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
[TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[31] = { ALU_OP0_NOP, tgsi_unsupported},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
- [33] = { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[35] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[31] = { ALU_OP0_NOP, tgsi_unsupported},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
- [33] = { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[35] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
[TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
[TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
[TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
+ [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
+ [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
+ [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
+ [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
[TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
};
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
[31] = { ALU_OP0_NOP, tgsi_unsupported},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
- [33] = { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[35] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},
[TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int},
[TGSI_OPCODE_U2D] = { ALU_OP1_UINT_TO_FLT, egcm_int_to_double},
[TGSI_OPCODE_DRSQ] = { ALU_OP2_RECIPSQRT_64, cayman_emit_double_instr},
+ [TGSI_OPCODE_U64SNE] = { ALU_OP0_NOP, egcm_u64sne },
+ [TGSI_OPCODE_U64ADD] = { ALU_OP0_NOP, egcm_u64add },
+ [TGSI_OPCODE_U64MUL] = { ALU_OP0_NOP, egcm_u64mul },
+ [TGSI_OPCODE_U64DIV] = { ALU_OP0_NOP, egcm_u64div },
[TGSI_OPCODE_LAST] = { ALU_OP0_NOP, tgsi_unsupported},
};
projects / mesa.git / blobdiff