nv30/shader: SSG, LIT only requires one source register

[mesa.git] / src / gallium / drivers / r600 / r600_shader.c

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index fa29b36f8f81446b31d2e7112f047fb28986dc3b..cd78104a010a97df32908cb2d70f792a731dd038 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -722,8 +722,8 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
                ctx->shader->input[i].name = d->Semantic.Name;
                ctx->shader->input[i].sid = d->Semantic.Index;
                ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]);
-               ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
-               ctx->shader->input[i].centroid = d->Declaration.Centroid;
+               ctx->shader->input[i].interpolate = d->Interp.Interpolate;
+               ctx->shader->input[i].centroid = d->Interp.Centroid;
                ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First;
                if (ctx->type == TGSI_PROCESSOR_FRAGMENT) {
                        switch (ctx->shader->input[i].name) {
@@ -749,7 +749,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
                ctx->shader->output[i].sid = d->Semantic.Index;
                ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]);
                ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First;
-               ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
+               ctx->shader->output[i].interpolate = d->Interp.Interpolate;
                ctx->shader->output[i].write_mask = d->Declaration.UsageMask;
                if (ctx->type == TGSI_PROCESSOR_VERTEX) {
                        switch (d->Semantic.Name) {
@@ -5154,7 +5154,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {80,                    0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PUSHA,     0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_POPA,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_CEIL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CEIL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
        {TGSI_OPCODE_I2F,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
        {TGSI_OPCODE_NOT,       0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
@@ -5220,16 +5220,16 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_CASE,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_DEFAULT,   0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_LOAD,      0, 0, tgsi_unsupported},
-       {TGSI_OPCODE_LOAD_MS,   0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE,    0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SAMPLE_I,  0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SAMPLE_I_MS, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_B,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_C,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_D,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_L,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_GATHER4,   0, 0, tgsi_unsupported},
-       {TGSI_OPCODE_RESINFO,   0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_UARL,      0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_r600_arl},
@@ -5328,7 +5328,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {80,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PUSHA,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_POPA,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
        {TGSI_OPCODE_I2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans},
        {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
@@ -5394,16 +5394,16 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_CASE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_DEFAULT,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_LOAD,      0, 0, tgsi_unsupported},
-       {TGSI_OPCODE_LOAD_MS,   0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE,    0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SAMPLE_I,      0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SAMPLE_I_MS,   0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_B,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_C,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_D,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_L,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_GATHER4,   0, 0, tgsi_unsupported},
-       {TGSI_OPCODE_RESINFO,   0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_UARL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},
@@ -5502,7 +5502,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {80,                    0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_PUSHA,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_POPA,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+       {TGSI_OPCODE_CEIL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL, tgsi_op2},
        {TGSI_OPCODE_I2F,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2},
        {TGSI_OPCODE_NOT,       0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2},
        {TGSI_OPCODE_TRUNC,     0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2},
@@ -5568,16 +5568,16 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
        {TGSI_OPCODE_CASE,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_DEFAULT,   0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
        {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-       {TGSI_OPCODE_LOAD,      0, 0, tgsi_unsupported},
-       {TGSI_OPCODE_LOAD_MS,   0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE,    0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SAMPLE_I,      0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SAMPLE_I_MS,   0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_B,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_C,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_C_LZ, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_D,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_L,  0, 0, tgsi_unsupported},
        {TGSI_OPCODE_GATHER4,   0, 0, tgsi_unsupported},
-       {TGSI_OPCODE_RESINFO,   0, 0, tgsi_unsupported},
+       {TGSI_OPCODE_SVIEWINFO, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_POS, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_SAMPLE_INFO, 0, 0, tgsi_unsupported},
        {TGSI_OPCODE_UARL,      0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT, tgsi_eg_arl},