goto error;
}
} else {
- if (sel->ir_type == PIPE_SHADER_IR_TGSI)
- sel->nir = tgsi_to_nir_noscreen(sel->tokens, &r600_nir_options);
+ if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
+ sel->nir = tgsi_to_nir(sel->tokens, ctx->screen, true);
+ /* Lower int64 ops because we have some r600 build-in shaders that use it */
+ if (!ctx->screen->get_param(ctx->screen, PIPE_CAP_DOUBLES)) {
+ NIR_PASS_V(sel->nir, nir_lower_regs_to_ssa);
+ NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar, NULL, NULL);
+ NIR_PASS_V(sel->nir, nir_lower_int64);
+ NIR_PASS_V(sel->nir, nir_opt_vectorize, NULL, NULL);
+ }
+ NIR_PASS_V(sel->nir, nir_lower_flrp, ~0, false);
+ }
nir_tgsi_scan_shader(sel->nir, &sel->info, true);
+
r = r600_shader_from_nir(rctx, shader, &key);
if (r) {
fprintf(stderr, "--Failed shader--------------------------------------------------\n");
#endif
for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
if (i->Src[j].Register.Dimension) {
- switch (i->Src[j].Register.File) {
- case TGSI_FILE_CONSTANT:
- case TGSI_FILE_HW_ATOMIC:
- break;
- case TGSI_FILE_INPUT:
- if (ctx->type == PIPE_SHADER_GEOMETRY ||
- ctx->type == PIPE_SHADER_TESS_CTRL ||
- ctx->type == PIPE_SHADER_TESS_EVAL)
- break;
- case TGSI_FILE_OUTPUT:
- if (ctx->type == PIPE_SHADER_TESS_CTRL)
- break;
- default:
- R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
- i->Src[j].Register.File,
- i->Src[j].Register.Dimension);
- return -EINVAL;
- }
+ switch (i->Src[j].Register.File) {
+ case TGSI_FILE_CONSTANT:
+ case TGSI_FILE_HW_ATOMIC:
+ break;
+ case TGSI_FILE_INPUT:
+ if (ctx->type == PIPE_SHADER_GEOMETRY ||
+ ctx->type == PIPE_SHADER_TESS_CTRL ||
+ ctx->type == PIPE_SHADER_TESS_EVAL)
+ break;
+ /* fallthrough */
+ case TGSI_FILE_OUTPUT:
+ if (ctx->type == PIPE_SHADER_TESS_CTRL)
+ break;
+ /* fallthrough */
+ default:
+ R600_ERR("unsupported src %d (file %d, dimension %d)\n", j,
+ i->Src[j].Register.File,
+ i->Src[j].Register.Dimension);
+ return -EINVAL;
+ }
}
}
for (j = 0; j < i->Instruction.NumDstRegs; j++) {
else {
if (name == TGSI_SEMANTIC_GENERIC) {
/* For generic params simply use sid from tgsi */
+ index = 9 + io->sid;
+ } else if (name == TGSI_SEMANTIC_TEXCOORD) {
index = io->sid;
} else {
/* For non-generic params - pack name and sid into 8 bits */
};
/* we need this to get a common lds index for vs/tcs/tes input/outputs */
-int r600_get_lds_unique_index(unsigned semantic_name, unsigned index, bool texcoord_semantics)
+int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
{
switch (semantic_name) {
case TGSI_SEMANTIC_POSITION:
case TGSI_SEMANTIC_CLIPDIST:
assert(index <= 1);
return 2 + index;
+ case TGSI_SEMANTIC_TEXCOORD:
+ return 4 + index;
case TGSI_SEMANTIC_GENERIC:
if (index <= 63-4)
- return 4 + index - (texcoord_semantics ? 0 : 9);
+ return 4 + index;
else
/* same explanation as in the default statement,
* the only user hitting this is st/nine.
break;
else if (d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ||
d->Semantic.Name == TGSI_SEMANTIC_TESSOUTER) {
- int param = r600_get_lds_unique_index(d->Semantic.Name, 0, false);
+ int param = r600_get_lds_unique_index(d->Semantic.Name, 0);
int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2;
unsigned temp_reg = r600_get_temp(ctx);
return r;
param = r600_get_lds_unique_index(name[first],
- index[first], false);
+ index[first]);
} else {
param = r600_get_lds_unique_index(name[reg.Register.Index],
- index[reg.Register.Index], false);
+ index[reg.Register.Index]);
}
/* add to base_addr - passed in temp_reg.x */
for (i = 0; i < ctx->shader->noutput; i++) {
struct r600_bytecode_alu alu;
int param = r600_get_lds_unique_index(ctx->shader->output[i].name,
- ctx->shader->output[i].sid, false);
+ ctx->shader->output[i].sid);
if (param) {
r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
int dreg = ctx->shader->output[output_idx].gpr;
int r;
- param = r600_get_lds_unique_index(name, 0, false);
+ param = r600_get_lds_unique_index(name, 0);
r = get_lds_offset0(ctx, 1, temp_reg, true);
if (r)
return r;